[PATCH v3 1/3] arm: socfpga: Consolidate dram_bank_mmu_setup()

[Sune Brian]

On Tue, May 12, 2026 at 2:50 PM <alif.zakuan.yuslaimi at altera.com> wrote:
>
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> Relocate the dram_bank_mmu_setup() implementation from misc_arria10.c to
> the common socfpga misc.c and update the function to correctly handle both
> pre-relocation and post-relocation cases for DRAM cache enabling for
> consistent MMU/dcache setup across Arria10 and CycloneV platforms.
>
> These changes help to improve maintainability and consistency of DRAM
> initialization as well as MMU configuration for Arria10 and CycloneV
> platforms.
>
> New Kconfig is introduced to enable this implementation only on the default
> Arria10 and CycloneV boards as this will increase the SPL size which
> will exceed some Gen5 devices' SPL size limit.
>
> Fixes: e26ecebc684b ("socfpga: arria10: Allow dcache_enable before relocation")
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---
>
> Changes in v3:
> - Removed 'select SPL_CACHE if SPL' Kconfig guard from this patch and
>   applied this condition alongside SOCFPGA_ECC_SUPPORT on patch 3
>
> Changes in v2:
> - Shared dram_bank_mmu_setup() is set as optional via Kconfig and defaulted
>   on only for the reference Arria10/CycloneV boards to avoid SPL overflows
>   on size-limited Gen5 defconfigs.
>
>  arch/arm/mach-socfpga/misc.c         | 31 ++++++++++++++++++++++++++++
>  arch/arm/mach-socfpga/misc_arria10.c | 26 -----------------------
>  2 files changed, 31 insertions(+), 26 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 1eef7893e54..80b054dcae9 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c

Tested-by: Brian Sune <briansune at gmail.com>

Testing environment:
- Latest repository
- Custom board 2G max capacity SoCFPGA Cyclone V can handle.
- SDMMC Boot

Both cold warm reset shows no issue:

Boot log:
U-Boot SPL 2026.07-rc2-00016-g36d4c6535808-dirty (May 14 2026 - 08:24:01 +0800)
DDRCAL: Scrubbing ECC RAM (2048 MiB).
DDRCAL: SDRAM-ECC initialized success with 1053 ms
Trying to boot from MMC1


U-Boot 2026.07-rc2-00016-g36d4c6535808-dirty (May 14 2026 - 08:24:01 +0800)

Thanks,
Brian

>