[PATCH v3 3/3] ddr: socfpga: Implement ECC DRAM scrubbing support for both Gen5/Arria10

[Sune Brian]

On Tue, May 12, 2026 at 2:50 PM <alif.zakuan.yuslaimi at altera.com> wrote:
>
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> Enable ECC scrubbing support for Gen5 by moving sdram_init_ecc_bits() from
> sdram_arria10.c to a new common file, sdram_soc32.c which is shared by both
> Arria10 and Gen5 devices. This makes ECC scrubbing support no longer
> exclusive only to Arria10.
>
> New Kconfig is introduced to enable this implementation only on the default
> Arria10 and CycloneV boards as this will increase the SPL size which
> will exceed some Gen5 devices' SPL size limit.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---
>
> Changes in v3:
> - Updated commit message
> - Removed legacy HW watchdog check in favor of current WDT DM for Gen5/Arria10
> - Dead code cleanups, indentation fixes
>
> Changes in v2:
> - ECC scrubbing is set as optional via Kconfig and defaulted on only for
>   the reference Arria10/CycloneV boards to avoid SPL overflows on
>   size-limited Gen5 defconfigs.
>
>  arch/arm/mach-socfpga/Kconfig      | 12 +++++
>  arch/arm/mach-socfpga/spl_a10.c    | 11 ++--
>  arch/arm/mach-socfpga/spl_gen5.c   | 10 +++-
>  drivers/ddr/altera/Makefile        |  4 +-
>  drivers/ddr/altera/sdram_arria10.c | 31 ++++-------
>  drivers/ddr/altera/sdram_gen5.c    | 39 ++++++++++++--
>  drivers/ddr/altera/sdram_soc32.c   | 85 ++++++++++++++++++++++++++++++
>  drivers/ddr/altera/sdram_soc32.h   | 15 ++++++
>  8 files changed, 172 insertions(+), 35 deletions(-)
>  create mode 100644 drivers/ddr/altera/sdram_soc32.c
>  create mode 100644 drivers/ddr/altera/sdram_soc32.h
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index b814e034ecd..dd71691b724 100644

Tested-by: Brian Sune <briansune at gmail.com>

Testing environment:
- Latest repository
- Custom board 2G max capacity SoCFPGA Cyclone V can handle.
- SDMMC Boot

Both cold warm reset shows no issue:

Boot log:
U-Boot SPL 2026.07-rc2-00016-g36d4c6535808-dirty (May 14 2026 - 08:24:01 +0800)
DDRCAL: Scrubbing ECC RAM (2048 MiB).
DDRCAL: SDRAM-ECC initialized success with 1053 ms
Trying to boot from MMC1


U-Boot 2026.07-rc2-00016-g36d4c6535808-dirty (May 14 2026 - 08:24:01 +0800)

Thanks,
Brian