[PATCH v3 2/2] riscv: Exclude ACLINT for TARGET_XILINX_MBV

[Michal Simek]

The Xilinx MicroBlaze V platform does not have an ACLINT (Advanced
Core Local Interruptor) hardware block. The timer functionality is
provided through a different mechanism.

Exclude both RISCV_ACLINT and SPL_RISCV_ACLINT from being implied
for TARGET_XILINX_MBV while keeping the default behavior for other
generic RISC-V targets that do have ACLINT hardware.

   spl/u-boot-spl: all -1382 data -360 rodata -200 text -822

Signed-off-by: Michal Simek <michal.simek at amd.com>
---

(no changes since v2)

Changes in v2:
- Separate platform defconfig from core Kconfig

 configs/xilinx_mbv32_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 67b7db94d745..82bbba6d0f00 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -20,6 +20,8 @@ CONFIG_SYS_CLK_FREQ=100000000
 CONFIG_BOOT_SCRIPT_OFFSET=0x0
 CONFIG_TARGET_XILINX_MBV=y
 # CONFIG_RISCV_ISA_F is not set
+# CONFIG_RISCV_ACLINT is not set
+# CONFIG_SPL_RISCV_ACLINT is not set
 # CONFIG_SPL_SMP is not set
 # CONFIG_AVAILABLE_HARTS is not set
 CONFIG_SPL_OPTIMIZE_INLINING=y
-- 
2.43.0

base-commit: 6267afe7f46f3ae1cd58671e57aae88646c835bd
branch: debian-sent3