[PATCH RFC 12/18] clk: rockchip: rk3568: Reduce code size for TPL build

[Pavel Golikov]

RK3568 has only 59.5Kb usable SRAM for TPL stage. Disable all clock
related functionality for TPL build. Clock driver can still be used to
get GRF syscon reference from it.

Signed-off-by: Pavel Golikov <paullo612 at ya.ru>
---
 drivers/clk/rockchip/clk_rk3568.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 199bb51fa6f..384d0c750d5 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -28,6 +28,7 @@ struct rk3568_pmuclk_plat {
 };
 #endif
 
+#if !IS_ENABLED(CONFIG_TPL_BUILD)
 #define RK3568_CPUCLK_RATE(_rate, _aclk_div, _pclk_div)		\
 {								\
 	.rate	= _rate##U,					\
@@ -2315,6 +2316,7 @@ static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv,
 
 	return rk3568_uart_get_rate(priv, clk_id);
 }
+#endif
 
 static ulong rk3568_clk_get_rate(struct clk *clk)
 {
@@ -2327,6 +2329,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
 	}
 
 	switch (clk->id) {
+#if !IS_ENABLED(CONFIG_TPL_BUILD)
 	case PLL_APLL:
 	case ARMCLK:
 		rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru,
@@ -2486,6 +2489,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
 	case CPLL_25M:
 		rate = rk3568_cpll_div_get_rate(priv, clk->id);
 		break;
+#endif
 	default:
 		return -ENOENT;
 	}
@@ -2504,6 +2508,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
 	}
 
 	switch (clk->id) {
+#if !IS_ENABLED(CONFIG_TPL_BUILD)
 	case PLL_APLL:
 	case ARMCLK:
 		if (priv->armclk_hz)
@@ -2673,6 +2678,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
 	case CPLL_25M:
 		ret = rk3568_cpll_div_set_rate(priv, clk->id, rate);
 		break;
+#endif
 	default:
 		return -ENOENT;
 	}
@@ -2681,6 +2687,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
 };
 
 #if (CONFIG_IS_ENABLED(OF_CONTROL)) || (!CONFIG_IS_ENABLED(OF_PLATDATA))
+#if !IS_ENABLED(CONFIG_TPL_BUILD)
 static int rk3568_gmac0_src_set_parent(struct clk *clk, struct clk *parent)
 {
 	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
@@ -2823,10 +2830,12 @@ static int rk3568_rkvdec_set_parent(struct clk *clk, struct clk *parent)
 
 	return 0;
 }
+#endif
 
 static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
 {
 	switch (clk->id) {
+#if !IS_ENABLED(CONFIG_TPL_BUILD)
 	case SCLK_GMAC0:
 		return rk3568_gmac0_src_set_parent(clk, parent);
 	case SCLK_GMAC1:
@@ -2848,6 +2857,7 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
 	case SCLK_GMAC1_RGMII_SPEED:
 	case SCLK_GMAC1_RMII_SPEED:
 		break;
+#endif
 	default:
 		return -ENOENT;
 	}
@@ -2864,6 +2874,7 @@ static struct clk_ops rk3568_clk_ops = {
 #endif
 };
 
+#if !IS_ENABLED(CONFIG_TPL_BUILD)
 static void rk3568_clk_init(struct rk3568_clk_priv *priv)
 {
 	int ret;
@@ -2903,18 +2914,14 @@ static void rk3568_clk_init(struct rk3568_clk_priv *priv)
 	priv->ppll_hz = rk3568_pmu_pll_get_rate(priv, PPLL);
 	priv->hpll_hz = rk3568_pmu_pll_get_rate(priv, HPLL);
 }
+#endif
 
 static int rk3568_clk_probe(struct udevice *dev)
 {
 	struct rk3568_clk_priv *priv = dev_get_priv(dev);
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct rk3568_clk_plat *plat = dev_get_plat(dev);
-#endif
+#if !IS_ENABLED(CONFIG_TPL_BUILD)
 	int ret;
 
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
-#endif
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 	if (IS_ERR(priv->grf))
 		return PTR_ERR(priv->grf);
@@ -2927,7 +2934,12 @@ static int rk3568_clk_probe(struct udevice *dev)
 		debug("%s clk_set_defaults failed %d\n", __func__, ret);
 	else
 		priv->sync_kernel = true;
+#endif
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3568_clk_plat *plat = dev_get_plat(dev);
 
+	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
+#endif
 	return 0;
 }
 

-- 
2.25.1