[PATCH v2] mtd: spi-nor: Add gd55lb02gf chips

[Takahiro.Kuwano at infineon.com]

> Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with
> the same read path flags.
> 
> SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's
> status register layout: the GD55LB02GF uses a 5-bit block protect
> field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet
> "Status Register Block Protection").
> 
> The generic stm-lock helpers drive only BP0..BP2 and assume SR1
> bit 5 is TB, but on this part SR1 bit 5 is BP3.
> Enabling either flag would leave BP3..BP4 unmanaged or corrupt
> BP3 on every lock op.
> A proper support needs a vendor specific lock callback, it is out
> of scope for this table update.
> 
> Signed-off-by: Vincent Jardin <vjardin at free.fr>
> Suggested-by: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
> 
> ---
> 
> Changes in v2:
> - Place the new entry next to gd55lb02ge with style matching the
>   neighbour.
> - Drop SPI_NOR_HAS_LOCK. Did not adopt SPI_NOR_HAS_TB from
>   gd55lb02ge: neither flag matches this chip's SR layout (see
>   comments for the BP0..BP4 / CMP rationale).
> 
>  drivers/mtd/spi/spi-nor-ids.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index c0fa98424aa..31a2ba49a87 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -231,6 +231,10 @@ const struct flash_info spi_nor_ids[] = {
>                      SECT_4K | SPI_NOR_QUAD_READ |
>                      SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>         },
> +       {
> +               INFO("gd55lb02gf", 0xc8601c, 0, 64 * 1024, 4096,
> +                    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)
> +       },
>  #endif
>  #ifdef CONFIG_SPI_FLASH_ISSI           /* ISSI */
>         /* ISSI */
> --
> 2.43.0
> 
> base-commit: bfe90a308a94caa9d855440683521ff04122ae2a
> branch: for-upstream/spi-nor-gd55lb02gf

Reviewed-by: Takahiro Kuwano <takahiro.kuwano at infineon.com>

Thanks!