[PATCH v8 09/12] pinctrl: airoha: add pin controller and gpio driver for EN7523 SoC
Mikhail Kshevetskiy
mikhail.kshevetskiy at iopsys.eu
Tue May 19 01:51:12 CEST 2026
This patch adds U-Boot pin controller and gpio driver for Airoha EN7523 SoC.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy at iopsys.eu>
Reviewed-by: David Lechner <dlechner at baylibre.com>
---
drivers/pinctrl/airoha/Kconfig | 5 +
drivers/pinctrl/airoha/Makefile | 1 +
drivers/pinctrl/airoha/pinctrl-en7523.c | 813 ++++++++++++++++++++++++
3 files changed, 819 insertions(+)
create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 5d3e29c8fd6..f5d948b27eb 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -10,6 +10,11 @@ config PINCTRL_AIROHA
select SYSCON
bool
+config PINCTRL_AIROHA_EN7523
+ bool "Airoha EN7523 pin controller and gpio driver"
+ depends on TARGET_EN7523
+ select PINCTRL_AIROHA
+
config PINCTRL_AIROHA_AN7581
bool "Airoha AN7581 pin controller and gpio driver"
depends on TARGET_AN7581
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index c8c99dd22f8..b90bd180591 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -2,5 +2,6 @@
obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
+obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
new file mode 100644
index 00000000000..e3db5560f35
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -0,0 +1,813 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo at kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson at genexis.eu>
+ * Author: Markus Gothe <markus.gothe at genexis.eu>
+ * Author: Matheus Sampaio Queiroga <srherobrine20 at gmail.com>
+ */
+#include "airoha-common.h"
+
+/*
+# Airoha EN7523 Pinctrl Driver
+
+## GPIO and Pin Configuration
+
+The EN7523 SoC features 39 physical pins that can be configured for various functions.
+Each pin can be configured with different electrical characteristics:
+
+## GPIO Pin Functions
+
+| GPIO Pin | Physical Pin | Primary Function | Alternate Functions |
+| :------: | ------------ | :-----------------: | :------------------------------------ |
+| GPIO0 | 12 | General purpose I/O | Reserved on EN7523 |
+| GPIO1 | 13 | General purpose I/O | Reserved on EN7523 |
+| GPIO2 | 14 | General purpose I/O | Reserved on EN7523 |
+| GPIO3 | 15 | General purpose I/O | Reserved on EN7523 |
+| GPIO4 | 16 | General purpose I/O | Reserved on EN7523 |
+| GPIO5 | 17 | General purpose I/O | Reserved on EN7523 |
+| GPIO6 | 18 | General purpose I/O | PCIE_RESET1_GPIO_MODE |
+| GPIO7 | 19 | General purpose I/O | - |
+| GPIO8 | 20 | General purpose I/O | I2C1 (SCL), SGMII_MDIO, PCM_SPI1_CS3 |
+| GPIO9 | 21 | General purpose I/O | I2C1 (SDA), SGMII_MDIO, TOD, SPI0_CS1 |
+| GPIO10 | 22 | General purpose I/O | PCM_SPI1_CS1 |
+| GPIO11 | 23 | General purpose I/O | PCM_SPI1_CS4 |
+| GPIO12 | 24 | General purpose I/O | PCM1, PCM_SPI1 |
+| GPIO13 | 25 | General purpose I/O | SIPO, SIPO_RCLK, NPU_UART |
+| GPIO14 | 26 | General purpose I/O | I2C0_SLAVE, PCM_SPI1_RESET, SPI0_QUAD |
+| GPIO15 | 27 | General purpose I/O | I2C0_SLAVE, PCM_SPI1_INT, SPI0_QUAD |
+| GPIO16 | 28 | General purpose I/O | LAN3_LED1, PCM2, I2S, PCM_SPI1 |
+| GPIO17 | 29 | General purpose I/O | LAN2_LED1, PCM2, I2S, PCM_SPI1 |
+| GPIO18 | 30 | General purpose I/O | LAN1_LED1, PCM2, I2S, PCM_SPI1 |
+| GPIO19 | 31 | General purpose I/O | LAN0_LED1, PCM2, I2S, PCM_SPI1 |
+| GPIO20 | 32 | General purpose I/O | UART2 (TX), SGMII_MDIO, PCM_SPI1_CS3 |
+| GPIO21 | 33 | General purpose I/O | UART2 (RX), SGMII_MDIO, TOD, SPI0_CS1 |
+| GPIO22 | 34 | General purpose I/O | - |
+| GPIO23 | 35 | General purpose I/O | - |
+| GPIO24 | 36 | General purpose I/O | PCM1, PCM_SPI1 |
+| GPIO25 | 37 | General purpose I/O | PCM1, PCM_SPI1 |
+| GPIO26 | 38 | General purpose I/O | PCM1, PCM_SPI1 |
+| GPIO27 | 39 | General purpose I/O | PCM1, PCM_SPI1, PCM_SPI1_CS2_156 |
+| GPIO28 | 40 | PAD_PCIE_RESET0 | GPIO28 |
+| GPIO29 | 41 | PAD_PCIE_RESET1 | GPIO29, PCM_SPI1_CS2_128 |
+
+### Function Groups
+
+#### Communication Interfaces
+
+- **UART2**: GPIO20 (TX), GPIO21 (RX)
+- **I2C1**: GPIO8 (SCL), GPIO9 (SDA)
+- **I2C0 Slave**: GPIO14, GPIO15
+- **MDIO**: GPIO8, GPIO9
+- **SPI Quad**: GPIO14, GPIO15
+- **SPI CS1**: GPIO21
+
+#### Audio Interfaces
+
+- **PCM1**: GPIO24, GPIO25, GPIO26, GPIO27
+- **PCM2**: GPIO16, GPIO17, GPIO18, GPIO19
+- **I2S**: GPIO16, GPIO17, GPIO18, GPIO19
+- **PCM_SPI1**: Various configurations with CS1-CS4 options
+
+#### Network Interfaces
+
+- **PON (Passive Optical Network)**: Defined in pon0_grp
+- **LAN LED Control**:
+ - LAN0: GPIO37 (LED0), GPIO19 (LED1)
+ - LAN1: GPIO36 (LED0), GPIO18 (LED1)
+ - LAN2: GPIO35 (LED0), GPIO17 (LED1)
+ - LAN3: GPIO34 (LED0), GPIO16 (LED1)
+
+#### Debug Interfaces
+
+- **JTAG UDI**: Defined in jtag_udi_grp
+- **JTAG DFD**: Defined in jtag_dfd_grp
+- **NPU UART**: GPIO13, GPIO38
+
+### Miscellaneous
+
+- **SIPO (Serial In, Parallel Out)**: GPIO13, GPIO38
+- **SIPO RCLK**: GPIO13, GPIO30, GPIO38
+- **TOD (Time of Day)**: GPIO21
+- **PCIe Reset as GPIO**: GPIO28 (PCIE_RESET0), GPIO29 (PCIE_RESET1)
+*/
+
+
+/* GPIO's */
+static const int en7523_gpio0_pins[] = { 0 };
+static const int en7523_gpio1_pins[] = { 1 };
+static const int en7523_gpio2_pins[] = { 2 };
+static const int en7523_gpio3_pins[] = { 3 };
+static const int en7523_gpio4_pins[] = { 4 };
+static const int en7523_gpio5_pins[] = { 5 };
+static const int en7523_gpio6_pins[] = { 6 };
+static const int en7523_gpio7_pins[] = { 7 };
+static const int en7523_gpio8_pins[] = { 8 };
+static const int en7523_gpio9_pins[] = { 9 };
+static const int en7523_gpio10_pins[] = { 10 };
+static const int en7523_gpio11_pins[] = { 11 };
+static const int en7523_gpio12_pins[] = { 12 };
+static const int en7523_gpio13_pins[] = { 13 };
+static const int en7523_gpio14_pins[] = { 14 };
+static const int en7523_gpio15_pins[] = { 15 };
+static const int en7523_gpio16_pins[] = { 16 };
+static const int en7523_gpio17_pins[] = { 17 };
+static const int en7523_gpio18_pins[] = { 18 };
+static const int en7523_gpio19_pins[] = { 19 };
+static const int en7523_gpio20_pins[] = { 20 };
+static const int en7523_gpio21_pins[] = { 21 };
+static const int en7523_gpio22_pins[] = { 22 };
+static const int en7523_gpio23_pins[] = { 23 };
+static const int en7523_gpio24_pins[] = { 24 };
+static const int en7523_gpio25_pins[] = { 25 };
+static const int en7523_gpio26_pins[] = { 26 };
+static const int en7523_gpio27_pins[] = { 27 };
+static const int en7523_gpio28_pins[] = { 28 };
+static const int en7523_gpio29_pins[] = { 29 };
+
+/* iomux */
+static const int en7523_uart2_pins[] = { 8, 9 };
+static const int en7523_mdio_pins[] = { 8, 9 };
+static const int en7523_i2c_slave_pins[] = { 2, 3 };
+static const int en7523_jtag_pins[] = { 22, 23, 24, 25, 26 };
+static const int en7523_sipo_pins[] = { 1, 18, 26 };
+static const int en7523_sipo_rclk_pins[] = { 18 };
+
+/* SPI */
+static const int en7523_spi_pins[] = { 4, 5, 6, 7 };
+static const int en7523_spi_cs1_pins[] = { 21 };
+static const int en7523_spi_quad_pins[] = { 14, 15 };
+
+/* PCM */
+static const int en7523_pcm1_pins[] = { 12, 13, 14, 15 };
+static const int en7523_pcm2_pins[] = { 4, 5, 6, 7 };
+static const int en7523_pcm_spi_cs1_pins[] = { 10 };
+static const int en7523_pcm_spi_cs2_pins[] = { 27 };
+static const int en7523_pcm_spi_cs3_pins[] = { 8 };
+static const int en7523_pcm_spi_cs4_pins[] = { 11 };
+static const int en7523_pcm_rst_pins[] = { 2 };
+static const int en7523_pcm_int_pins[] = { 3 };
+
+/* PCIE Resets */
+static const int en7523_pcie_reset0_pins[] = { 28 };
+static const int en7523_pcie_reset1_pins[] = { 29 };
+
+static struct pinctrl_pin_desc en7523_pinctrl_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+ PINCTRL_PIN(15, "gpio15"),
+ PINCTRL_PIN(16, "gpio16"),
+ PINCTRL_PIN(17, "gpio17"),
+ PINCTRL_PIN(18, "gpio18"),
+ PINCTRL_PIN(19, "gpio19"),
+ PINCTRL_PIN(20, "gpio20"),
+ PINCTRL_PIN(21, "gpio21"),
+ PINCTRL_PIN(22, "gpio22"),
+ PINCTRL_PIN(23, "gpio23"),
+ PINCTRL_PIN(24, "gpio24"),
+ PINCTRL_PIN(25, "gpio25"),
+ PINCTRL_PIN(26, "gpio26"),
+ PINCTRL_PIN(27, "gpio27"),
+ PINCTRL_PIN(28, "pcie_reset0"),
+ PINCTRL_PIN(29, "pcie_reset1"),
+ PINCTRL_PIN(30, "gpio30"),
+ PINCTRL_PIN(31, "gpio31"),
+ PINCTRL_PIN(32, "gpio32"),
+ PINCTRL_PIN(33, "gpio33"),
+ PINCTRL_PIN(34, "gpio34"),
+ PINCTRL_PIN(35, "gpio35"),
+ PINCTRL_PIN(36, "gpio36"),
+ PINCTRL_PIN(37, "gpio37"),
+ PINCTRL_PIN(38, "gpio38"),
+ PINCTRL_PIN(39, "gpio39"),
+ PINCTRL_PIN(40, "gpio40"),
+ PINCTRL_PIN(41, "gpio41"),
+ PINCTRL_PIN(42, "gpio42"),
+ PINCTRL_PIN(43, "gpio43"),
+ PINCTRL_PIN(44, "gpio44"),
+ PINCTRL_PIN(45, "gpio45"),
+ PINCTRL_PIN(46, "gpio46"),
+ PINCTRL_PIN(47, "gpio47"),
+ PINCTRL_PIN(48, "gpio48"),
+ PINCTRL_PIN(49, "gpio49"),
+ PINCTRL_PIN(50, "gpio50"),
+ PINCTRL_PIN(51, "gpio51"),
+ PINCTRL_PIN(52, "gpio52"),
+ PINCTRL_PIN(53, "gpio53"),
+ PINCTRL_PIN(54, "gpio54"),
+ PINCTRL_PIN(55, "gpio55"),
+ PINCTRL_PIN(56, "gpio56"),
+ PINCTRL_PIN(57, "gpio57"),
+ PINCTRL_PIN(58, "gpio58"),
+ PINCTRL_PIN(59, "gpio59"),
+ PINCTRL_PIN(60, "gpio60"),
+ PINCTRL_PIN(61, "gpio61"),
+ PINCTRL_PIN(62, "gpio62"),
+ PINCTRL_PIN(63, "gpio63"),
+};
+
+static const char *const en7523_uart2_groups[] = { "uart2" };
+static const char *const en7523_mdio_groups[] = { "mdio" };
+static const char *const en7523_i2c_slave_groups[] = { "i2c_slave" };
+static const char *const en7523_jtag_groups[] = { "jtag" };
+static const char *const en7523_pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1"
+};
+static const char *const en7523_sipo_groups[] = {
+ "sipo", "sipo_rclk"
+};
+static const char *const en7523_pcm_groups[] = {
+ "pcm1", "pcm2", "pcm_rst", "pcm_int"
+};
+static const char *const en7523_slic_spi_groups[] = {
+ "pcm_spi_cs1", "pcm_spi_cs2", "pcm_spi_cs3", "pcm_spi_cs4"
+};
+static const char *const en7523_spi_groups[] = {
+ "spi", "spi_quad", "spi_cs1"
+};
+static const char *const en7523_pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
+ "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
+ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
+ "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
+ "gpio28", "gpio29",
+};
+static const char *const en7523_phy1_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const en7523_phy2_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const en7523_phy3_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const en7523_phy4_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const en7523_phy1_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const en7523_phy2_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const en7523_phy3_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const en7523_phy4_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+
+static const struct airoha_pinctrl_func_group en7523_uart2_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK, GPIO_UART2_MODE_MASK },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_2ND_I2C_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MODE },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_i2c_slave_func_group[] = {
+ {
+ .name = "i2c_slave",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_2ND_I2C_MODE,
+ GPIO_I2C_SLAVE_MODE_MODE,
+ GPIO_I2C_SLAVE_MODE_MODE },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_jtag_func_group[] = {
+ {
+ .name = "jtag",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK, JTAG_UDI_EN_MASK },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK, GPIO_PCIE_RESET0_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "pcie_reset1",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK, GPIO_PCIE_RESET1_MASK },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "sipo_rclk",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK, GPIO_PCM1_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "pcm2",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK, GPIO_PCM2_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "pcm_rst",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK, GPIO_PCM_RESET_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "pcm_int",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK, GPIO_PCM_INT_MODE_MASK },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_spi_func_group[] = {
+ {
+ .name = "spi",
+ .regmap_size = 0,
+ },
+ {
+ .name = "spi_quad",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "spi_cs1",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK, GPIO_SPI_CS1_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "spi_cs2",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS2_MODE_MASK, GPIO_SPI_CS2_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "spi_cs3",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS3_MODE_MASK, GPIO_SPI_CS3_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "spi_cs4",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS4_MODE_MASK, GPIO_SPI_CS4_MODE_MASK },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_slic_spi_func_group[] = {
+ {
+ .name = "slic_spi_cs1",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK, GPIO_PCM_SPI_CS1_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "slic_spi_cs2",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "slic_spi_cs3",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK, GPIO_PCM_SPI_CS3_MODE_MASK },
+ .regmap_size = 1,
+ },
+ {
+ .name = "slic_spi_cs4",
+ .regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK, GPIO_PCM_SPI_CS4_MODE_MASK },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group en7523_pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group en7523_phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct pingroup en7523_pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("uart2", en7523_uart2),
+ PINCTRL_PIN_GROUP("mdio", en7523_mdio),
+ PINCTRL_PIN_GROUP("i2c_slave", en7523_i2c_slave),
+ PINCTRL_PIN_GROUP("jtag", en7523_jtag),
+ PINCTRL_PIN_GROUP("sipo", en7523_sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", en7523_sipo_rclk),
+ PINCTRL_PIN_GROUP("pcm1", en7523_pcm1),
+ PINCTRL_PIN_GROUP("pcm2", en7523_pcm2),
+ PINCTRL_PIN_GROUP("pcm_rst", en7523_pcm_rst),
+ PINCTRL_PIN_GROUP("pcm_int", en7523_pcm_int),
+ PINCTRL_PIN_GROUP("spi", en7523_spi),
+ PINCTRL_PIN_GROUP("spi_quad", en7523_spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", en7523_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", en7523_pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2", en7523_pcm_spi_cs2),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", en7523_pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", en7523_pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("pcie_reset0", en7523_pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", en7523_pcie_reset1),
+ PINCTRL_PIN_GROUP("gpio0", en7523_gpio0),
+ PINCTRL_PIN_GROUP("gpio1", en7523_gpio1),
+ PINCTRL_PIN_GROUP("gpio2", en7523_gpio2),
+ PINCTRL_PIN_GROUP("gpio3", en7523_gpio3),
+ PINCTRL_PIN_GROUP("gpio4", en7523_gpio4),
+ PINCTRL_PIN_GROUP("gpio5", en7523_gpio5),
+ PINCTRL_PIN_GROUP("gpio6", en7523_gpio6),
+ PINCTRL_PIN_GROUP("gpio7", en7523_gpio7),
+ PINCTRL_PIN_GROUP("gpio8", en7523_gpio8),
+ PINCTRL_PIN_GROUP("gpio9", en7523_gpio9),
+ PINCTRL_PIN_GROUP("gpio10", en7523_gpio10),
+ PINCTRL_PIN_GROUP("gpio11", en7523_gpio11),
+ PINCTRL_PIN_GROUP("gpio12", en7523_gpio12),
+ PINCTRL_PIN_GROUP("gpio13", en7523_gpio13),
+ PINCTRL_PIN_GROUP("gpio14", en7523_gpio14),
+ PINCTRL_PIN_GROUP("gpio15", en7523_gpio15),
+ PINCTRL_PIN_GROUP("gpio16", en7523_gpio16),
+ PINCTRL_PIN_GROUP("gpio17", en7523_gpio17),
+ PINCTRL_PIN_GROUP("gpio18", en7523_gpio18),
+ PINCTRL_PIN_GROUP("gpio19", en7523_gpio19),
+ PINCTRL_PIN_GROUP("gpio20", en7523_gpio20),
+ PINCTRL_PIN_GROUP("gpio21", en7523_gpio21),
+ PINCTRL_PIN_GROUP("gpio22", en7523_gpio22),
+ PINCTRL_PIN_GROUP("gpio23", en7523_gpio23),
+ PINCTRL_PIN_GROUP("gpio24", en7523_gpio24),
+ PINCTRL_PIN_GROUP("gpio25", en7523_gpio25),
+ PINCTRL_PIN_GROUP("gpio26", en7523_gpio26),
+ PINCTRL_PIN_GROUP("gpio27", en7523_gpio27),
+ PINCTRL_PIN_GROUP("gpio28", en7523_gpio28),
+ PINCTRL_PIN_GROUP("gpio29", en7523_gpio29),
+};
+
+static const struct airoha_pinctrl_func en7523_pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("uart", en7523_uart2),
+ PINCTRL_FUNC_DESC("mdio", en7523_mdio),
+ PINCTRL_FUNC_DESC("i2c", en7523_i2c_slave),
+ PINCTRL_FUNC_DESC("jtag", en7523_jtag),
+ PINCTRL_FUNC_DESC("pcie_reset", en7523_pcie_reset),
+ PINCTRL_FUNC_DESC("sipo", en7523_sipo),
+ PINCTRL_FUNC_DESC("pcm", en7523_pcm),
+ PINCTRL_FUNC_DESC("spi", en7523_spi),
+ PINCTRL_FUNC_DESC("slic_spi", en7523_slic_spi),
+ PINCTRL_FUNC_DESC("pwm", en7523_pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", en7523_phy1_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", en7523_phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led0", en7523_phy2_led0),
+ PINCTRL_FUNC_DESC("phy2_led1", en7523_phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led0", en7523_phy3_led0),
+ PINCTRL_FUNC_DESC("phy3_led1", en7523_phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led0", en7523_phy4_led0),
+ PINCTRL_FUNC_DESC("phy4_led1", en7523_phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf en7523_pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, EN7523_SPI_CS0_PU_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, EN7523_SPI_CLK_PU_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, EN7523_SPI_MOSI_PU_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, EN7523_SPI_MISO_PU_MASK),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7523_pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, EN7523_SPI_CS0_PD_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, EN7523_SPI_CLK_PD_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, EN7523_SPI_MOSI_PD_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, EN7523_SPI_MISO_PD_MASK),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7523_pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, EN7523_SPI_CS0_E2_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, EN7523_SPI_CLK_E2_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, EN7523_SPI_MOSI_E2_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, EN7523_SPI_MISO_E2_MASK),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7523_pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, EN7523_SPI_CS0_E4_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, EN7523_SPI_CLK_E4_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, EN7523_SPI_MOSI_E4_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, EN7523_SPI_MISO_E4_MASK),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7523_pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(28, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(29, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data en7523_pinctrl_match_data = {
+ .gpio_offs = 0,
+ .gpio_pin_cnt = 64,
+ .pins = en7523_pinctrl_pins,
+ .num_pins = ARRAY_SIZE(en7523_pinctrl_pins),
+ .grps = en7523_pinctrl_groups,
+ .num_grps = ARRAY_SIZE(en7523_pinctrl_groups),
+ .funcs = en7523_pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(en7523_pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = en7523_pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(en7523_pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = en7523_pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(en7523_pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = en7523_pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(en7523_pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = en7523_pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(en7523_pinctrl_drive_e4_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+ .confs = en7523_pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(en7523_pinctrl_pcie_rst_od_conf),
+ },
+ },
+};
+
+static const struct udevice_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,en7523-pinctrl",
+ .data = (uintptr_t)&en7523_pinctrl_match_data },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(airoha_en7523_pinctrl) = {
+ .name = "airoha-en7523-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(airoha_pinctrl_of_match),
+ .probe = airoha_pinctrl_probe,
+ .bind = airoha_pinctrl_bind,
+ .priv_auto = sizeof(struct airoha_pinctrl),
+ .ops = &airoha_pinctrl_ops,
+};
--
2.53.0
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