[PATCH 2/6] arm: ti: omap: Extract common clock definitions
Bastien Curutchet
bastien.curutchet at bootlin.com
Tue May 19 08:45:39 CEST 2026
Lots of clock definitions are common to OMAP3, OMAP4 and OMAP5. So the
same macros are defined both in arch-am33xx/clock.h and in
arch-omap5/clock.h. Upcoming support for OMAP4 will again need the same
macros.
Group these common macro definitions into a common omap_clock header
shared across the OMAP2+ families.
Signed-off-by: Bastien Curutchet <bastien.curutchet at bootlin.com>
---
arch/arm/include/asm/arch-am33xx/clock.h | 43 +----------
arch/arm/include/asm/arch-omap5/clock.h | 101 +-----------------------
arch/arm/include/asm/ti-common/omap_clock.h | 114 ++++++++++++++++++++++++++++
3 files changed, 117 insertions(+), 141 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 13960db2fbd..80b0707131f 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -12,31 +12,10 @@
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/hardware.h>
+#include <asm/ti-common/omap_clock.h>
#define LDELAY 1000000
-/*CM_<clock_domain>__CLKCTRL */
-#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
-#define CD_CLKCTRL_CLKTRCTRL_MASK 3
-
-#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
-#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
-#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
-
-/* CM_<clock_domain>_<module>_CLKCTRL */
-#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
-#define MODULE_CLKCTRL_MODULEMODE_MASK 3
-#define MODULE_CLKCTRL_IDLEST_SHIFT 16
-#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
-
-#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
-#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
-
-#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
-#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
-#define MODULE_CLKCTRL_IDLEST_IDLE 2
-#define MODULE_CLKCTRL_IDLEST_DISABLED 3
-
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
@@ -53,26 +32,6 @@
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
-#define CM_CLKMODE_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
-
-#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
-
-#define DPLL_EN_STOP 1
-#define DPLL_EN_MN_BYPASS 4
-#define DPLL_EN_LOW_POWER_BYPASS 5
-#define DPLL_EN_FAST_RELOCK_BYPASS 6
-#define DPLL_EN_LOCK 7
-
-/* CM_IDLEST_DPLL fields */
-#define ST_DPLL_CLK_MASK 1
-
-/* CM_CLKSEL_DPLL */
-#define CM_CLKSEL_DPLL_M_SHIFT 8
-#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
-#define CM_CLKSEL_DPLL_N_SHIFT 0
-#define CM_CLKSEL_DPLL_N_MASK 0x7F
/* CM_SSC_DELTAM_DPLL */
#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index aaa5e573115..02dcc0e4356 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -9,6 +9,8 @@
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
+#include <asm/ti-common/omap_clock.h>
+
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
* loop, allow for a minimum of 2 ms wait (in reality the wait will be
@@ -19,7 +21,6 @@
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
-#define CM_DLL_CTRL_NO_OVERRIDE 0
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
@@ -32,20 +33,6 @@
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
-#define CM_CLKMODE_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
-
-#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
-
-#define DPLL_EN_STOP 1
-#define DPLL_EN_MN_BYPASS 4
-#define DPLL_EN_LOW_POWER_BYPASS 5
-#define DPLL_EN_FAST_RELOCK_BYPASS 6
-#define DPLL_EN_LOCK 7
-
-/* CM_IDLEST_DPLL fields */
-#define ST_DPLL_CLK_MASK 1
/* SGX */
#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
@@ -54,24 +41,6 @@
/* CM_CLKSEL_DPLL */
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
-#define CM_CLKSEL_DPLL_M_SHIFT 8
-#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
-#define CM_CLKSEL_DPLL_N_SHIFT 0
-#define CM_CLKSEL_DPLL_N_MASK 0x7F
-#define CM_CLKSEL_DCC_EN_SHIFT 22
-#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
-
-/* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
-
-/* CM_CLKSEL_CORE */
-#define CLKSEL_CORE_SHIFT 0
-#define CLKSEL_L3_SHIFT 4
-#define CLKSEL_L4_SHIFT 8
-
-#define CLKSEL_CORE_X2_DIV_1 0
-#define CLKSEL_L3_CORE_DIV_2 1
-#define CLKSEL_L4_L3_DIV_2 1
/* CM_ABE_PLL_REF_CLKSEL */
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
@@ -91,57 +60,12 @@
#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
-/* CM_SHADOW_FREQ_CONFIG1 */
-#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
-#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
-#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
-
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
-
-#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
-#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
-
-/*CM_<clock_domain>__CLKCTRL */
-#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
-#define CD_CLKCTRL_CLKTRCTRL_MASK 3
-
-#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
-#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
-#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
-#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
-
-/* CM_<clock_domain>_<module>_CLKCTRL */
-#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
-#define MODULE_CLKCTRL_MODULEMODE_MASK 3
-#define MODULE_CLKCTRL_IDLEST_SHIFT 16
-#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
-
-#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
-#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
-#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
-
-#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
-#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
-#define MODULE_CLKCTRL_IDLEST_IDLE 2
-#define MODULE_CLKCTRL_IDLEST_DISABLED 3
-
-/* CM_L4PER_GPIO4_CLKCTRL */
-#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_L3INIT_HSMMCn_CLKCTRL */
-#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
-
/* CM_IPU1_IPU1_CLKCTRL CLKSEL MASK */
#define IPU1_CLKCTRL_CLKSEL_MASK BIT(24)
/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-/* CM_WKUP_GPTIMER1_CLKCTRL */
-#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
-
/* CM_CAM_ISS_CLKCTRL */
#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
@@ -181,12 +105,6 @@
/* CM_L3INIT_OCP2SCP1_CLKCTRL */
#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
-/* CM_MPU_MPU_CLKCTRL */
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
-
/* CM_WKUPAON_SCRM_CLKCTRL */
#define OPTFCLKEN_SCRM_PER_SHIFT 9
#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
@@ -201,9 +119,6 @@
#define RSTTIME1_SHIFT 0
#define RSTTIME1_MASK (0x3ff << 0)
-/* Clock frequencies */
-#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-
/* CTRL_CORE_SRCOMP_NORTH_SIDE */
#define USB2PHY_DISCHGDET (1 << 29)
#define USB2PHY_AUTORESUME_EN (1 << 30)
@@ -399,16 +314,4 @@
/* CKO buffer control */
#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28)
-/* AUXCLKx reg fields */
-#define AUXCLK_ENABLE_MASK (1 << 8)
-#define AUXCLK_SRCSELECT_SHIFT 1
-#define AUXCLK_SRCSELECT_MASK (3 << 1)
-#define AUXCLK_CLKDIV_SHIFT 16
-#define AUXCLK_CLKDIV_MASK (0xF << 16)
-
-#define AUXCLK_SRCSELECT_SYS_CLK 0
-#define AUXCLK_SRCSELECT_CORE_DPLL 1
-#define AUXCLK_SRCSELECT_PER_DPLL 2
-#define AUXCLK_SRCSELECT_ALTERNATE 3
-
#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/ti-common/omap_clock.h b/arch/arm/include/asm/ti-common/omap_clock.h
new file mode 100644
index 00000000000..4a37b0bc8c3
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/omap_clock.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _OMAP_CLOCK_H_
+#define _OMAP_CLOCK_H_
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
+
+#define DPLL_EN_STOP 1
+#define DPLL_EN_MN_BYPASS 4
+#define DPLL_EN_LOW_POWER_BYPASS 5
+#define DPLL_EN_FAST_RELOCK_BYPASS 6
+#define DPLL_EN_LOCK 7
+
+#define DPLL_NO_LOCK 0
+#define DPLL_LOCK 1
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK 1
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT 0
+#define CLKSEL_L3_SHIFT 4
+#define CLKSEL_L4_SHIFT 8
+
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_NO_OVERRIDE 0
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_N_SHIFT 0
+#define CM_CLKSEL_DPLL_N_MASK 0x7F
+#define CM_CLKSEL_DPLL_M_SHIFT 8
+#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
+#define CM_CLKSEL_DCC_EN_SHIFT 22
+#define CM_CLKSEL_DCC_EN_MASK BIT(22)
+
+#define CLKSEL_CORE_X2_DIV_1 0
+#define CLKSEL_L3_CORE_DIV_2 1
+#define CLKSEL_L4_L3_DIV_2 1
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
+#define CD_CLKCTRL_CLKTRCTRL_MASK 3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
+#define MODULE_CLKCTRL_MODULEMODE_MASK 3
+#define MODULE_CLKCTRL_IDLEST_SHIFT 16
+#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
+#define MODULE_CLKCTRL_IDLEST_IDLE 2
+#define MODULE_CLKCTRL_IDLEST_DISABLED 3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK BIT(8)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK BIT(24)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK BIT(24)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_IND_38_4_MHZ 6
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK BIT(8)
+#define AUXCLK_SRCSELECT_SHIFT 1
+#define AUXCLK_SRCSELECT_MASK (3 << 1)
+#define AUXCLK_CLKDIV_SHIFT 16
+#define AUXCLK_CLKDIV_MASK (0xF << 16)
+#define AUXCLK_CLKDIV_2 1
+
+#define AUXCLK_SRCSELECT_SYS_CLK 0
+#define AUXCLK_SRCSELECT_CORE_DPLL 1
+#define AUXCLK_SRCSELECT_PER_DPLL 2
+#define AUXCLK_SRCSELECT_ALTERNATE 3
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK BIT(26)
+
+#endif /* _OMAP_CLOCK_H_ */
--
2.54.0
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