[PATCH v3 0/4] rockchip: PCIe gated reference clock support

[Daniele Briguglio]

The rk3588-rock-5-itx u-boot dtsi describes the PCIe reference
clocks (pcie30x4_refclk, pcie30x2_refclk on the M.2 M-key slots)
as "gated-fixed-clock" instances supplied by regulators.  Drive
those refclks from u-boot so the PCIe PHY can lock its PLL.

v1 [1] worked around the lack of a "gated-fixed-clock" driver in
u-boot by dropping the refclk references from pcie3x4/pcie3x2 in
a board-local dtsi override.  Jonas pointed out that the u-boot
dtsi is propagated to the OS via EFI handoff, making the dtsi
override approach brittle.

v2 [2] added a proper UCLASS_CLK driver for "gated-fixed-clock"
and enabled it in the rock-5-itx defconfig.  Jonas tested v2 on a
radxa rock-3b (RK3568) and surfaced:

  - an ordering bug in pcie_dw_rockchip: clk_enable_bulk() runs
    after generic_phy_init() and generic_phy_power_on(), so the
    PHY tries to lock its PLL before the gated refclk is
    enabled.  On boards where the refclk supply is
    regulator-always-on (the universal pattern in the in-tree
    DTs) this is masked; on rock-3b the PI6C supply is gated and
    the PHY init times out.
  - two stray clk_release_bulk() calls.  clk_release_bulk() is
    not a memory release (the bulk array is devm-allocated); it
    loops clk_disable() over the bulk.  In parse_dt() the clocks
    are acquired but never enabled, so the call disables clocks
    that are off.  In probe() after init_port() failure the
    inner err_disable_clks path balances the enable, so the
    outer call is a double-disable.  With the new gated-fixed-
    clock driver both cases desync the regulator enable_count,
    which on rock-5-itx with one M.2 populated would pull power
    from the populated slot when the empty one fails.

v3 keeps the v2 driver (plus the MAINTAINERS entry I forgot in
v2), fixes pcie_dw_rockchip, and switches the per-board defconfig
knob to a Kconfig imply so other boards pick up the driver
automatically as their DTs move to the binding.

Changes since v2:
  - patch 1: add MAINTAINERS entry for drivers/clk/clk-gated-fixed.c
  - new patch 2: pci: pcie_dw_rockchip: enable clocks before PHY init
  - new patch 3: pci: pcie_dw_rockchip: drop clk_release_bulk calls
  - new patch 4: pci: pcie_dw_rockchip: imply CLK_GATED_FIXED and
    switch PHY to imply
  - dropped the rock-5-itx defconfig patch (Kconfig imply pulls
    CLK_GATED_FIXED in automatically)

Testing:
  - patch 1 validated end-to-end on a NanoPC T6 LTS via the
    synthetic-DT approach Jonas suggested: a fake
    "gated-fixed-clock" node with a fake "regulator-fixed" supply
    injected into the board's u-boot dtsi and wired as an
    additional "ref" clock of pcie3x4.  Probe and enable trigger
    when pcie_dw_rockchip runs clk_enable_bulk, and NVMe
    enumerates through the synthetic refclk path.
  - patches 2 and 3 reported and validated by Jonas on radxa
    rock-3b (RK3568) where the PI6C refclk supply is gated and
    the regulator enable_count must stay balanced.
  - I don't have free access to a rock-5-itx at the moment (the
    one I maintain serves a production mirror), so v3 has been
    build-tested only on the real target.

[1] https://lore.kernel.org/u-boot/20260518-rock-5-itx-pcie-refclk-dtsi-v1-1-faf8626039fc@superkali.me/
[2] https://lore.kernel.org/u-boot/20260519-rock-5-itx-pcie-refclk-dtsi-v2-0-738b67857cac@superkali.me/

Signed-off-by: Daniele Briguglio <hello at superkali.me>
---
Daniele Briguglio (4):
      clk: add gated-fixed-clock driver
      pci: pcie_dw_rockchip: enable clocks before PHY init
      pci: pcie_dw_rockchip: drop clk_release_bulk calls
      pci: pcie_dw_rockchip: imply CLK_GATED_FIXED and switch PHY to imply

 MAINTAINERS                    |  5 +++
 drivers/clk/Kconfig            |  9 +++++
 drivers/clk/Makefile           |  1 +
 drivers/clk/clk-gated-fixed.c  | 84 ++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/Kconfig            |  3 +-
 drivers/pci/pcie_dw_rockchip.c | 23 ++++++------
 6 files changed, 112 insertions(+), 13 deletions(-)
---
base-commit: 38dbe637c9dfcadbd1bc201bfbb27f96b2ad525a
change-id: 20260518-rock-5-itx-pcie-refclk-dtsi-17ad4b21df1d

Best regards,
--  
Daniele Briguglio <hello at superkali.me>