[RFC PATCH v1 11/14] ram: rockchip: rk3576: add LPDDR5 timing table placeholder (2133 MHz)
Johan Axelsson
johan.axelsson at proton.me
Mon May 25 03:29:41 CEST 2026
Add sdram-rk3576-lpddr5-detect-2133.inc: a compileable timing table
for LPDDR5 at PHY 2x clock = 2133 MHz (CK = 1067 MHz, WCK = 4267 MHz,
data rate ≈ LPDDR5-8533).
All timing register values are TRM reset defaults and are NOT correct
for 1067 MHz LPDDR5 operation. The file exists so the driver compiles
with CONFIG_RAM_ROCKCHIP_LPDDR5=y. Hardware bring-up will fail until
the timing values are replaced with values derived from:
- JEDEC JESD209-5B LPDDR5 timing for the target speed grade
- Synopsys uMCTL2 SRS field encoding rules
- The actual DRAM part number and its timing datasheet
Correctly set:
- mstr0 = 0x01080040 (BIT(6)=lpddr5 | 1 rank | BL16 | full BW)
- cap_info: 8 GB LPDDR5, 2 channels × 4 GB, 2^17 rows
This is the primary timing table target for the Flipper One board
(8 GB LPDDR5). "2133" in the filename is the PHY 2x clock in MHz,
not the data rate.
Signed-off-by: Johan Axelsson <johan.axelsson at proton.me>
---
.../sdram-rk3576-lpddr5-detect-2133.inc | 174 ++++++++++++++++++
1 file changed, 174 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rk3576-lpddr5-detect-2133.inc
diff --git a/drivers/ram/rockchip/sdram-rk3576-lpddr5-detect-2133.inc b/drivers/ram/rockchip/sdram-rk3576-lpddr5-detect-2133.inc
new file mode 100644
index 00000000000..324eb3c6b09
--- /dev/null
+++ b/drivers/ram/rockchip/sdram-rk3576-lpddr5-detect-2133.inc
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RK3576 LPDDR5 timing table — PHY 2x clock 2133 MHz (CK = 1067 MHz,
+ * WCK = 4267 MHz, data rate ≈ LPDDR5-8533).
+ *
+ * PLACEHOLDER — timing register values below are TRM reset defaults
+ * and are NOT correct for 1067 MHz LPDDR5 operation. Hardware bring-up
+ * will fail until these are replaced with values calculated from:
+ *
+ * 1. JEDEC JESD209-5B LPDDR5 timing parameters for the target speed grade
+ * 2. Synopsys uMCTL2 Software Requirements Specification (SRS) field
+ * encoding rules (wr2pre, t_ras_min, RL/WL, tRFC, tDFI*, …)
+ * 3. The actual DRAM part number fitted on the target board and its
+ * timing datasheet (Flipper One: 8 GB, 2 channels, x32 per channel)
+ *
+ * Specifically wrong at 1067 MHz:
+ * dramset1tmg0.t_ras_min TRM reset = 15 cyc (14 ns); JEDEC min = 42 ns
+ * dramset1tmg0.wr2pre needs WL + BL/2 + tWR calculation
+ * dfitmg0/1 need tDFI_WRDATA, tDFI_RDDATA_EN for LP5 PHY
+ * initmr0–3 LP5 MR1/MR2/MR3/MR11 for 1067 MHz RL/WL/CK-ratio
+ * rfshset1tmg0.t_rfc_min needs LP5 die density (8 Gbit ≈ 210 ns)
+ *
+ * W9 work item. This file exists so the driver compiles with
+ * CONFIG_RAM_ROCKCHIP_LPDDR5=y.
+ */
+
+/*
+ * Shared per-frequency timing block (all four FREQ banks use the same
+ * placeholder values for now; a real table would differentiate them).
+ */
+#define LP5_2133_FREQ_TMG \
+{ \
+ /* \
+ * SDRAM timing — TRM reset values (sdram_pctl_rk3576.h). \
+ * Replace every field before hardware testing (see header). \
+ */ \
+ .dramset1tmg0 = 0x0F101B0F, /* t_ras_min/max, t_faw, wr2pre */\
+ .dramset1tmg1 = 0x00080414, /* t_rc, rd2pre, t_xp */ \
+ .dramset1tmg2 = 0x0305060D, /* wr2rd, rd2wr, read_lat, wr_lat */\
+ .dramset1tmg3 = 0x00040404, /* t_mr{d,mod,w} */ \
+ .dramset1tmg4 = 0x05040405, /* t_rp, t_rrd, t_ccd, t_rcd */ \
+ .dramset1tmg5 = 0x05050403, /* t_cke, t_ckesr, t_cksre, t_cksrx */\
+ .dramset1tmg6 = 0x00000005, /* t_ckcsx */ \
+ .dramset1tmg7 = 0x00000000, \
+ .dramset1tmg8 = 0x00004405, /* t_xs_{abort,fast}_x32 */ \
+ .dramset1tmg9 = 0x0004040D, /* t_dqsck_max, t_crd2wr */ \
+ .dramset1tmg12 = 0x00020000, /* t_cmdcke, t_mrd_pda */ \
+ .dramset1tmg13 = 0x1C200004, /* t_ppd, t_ccd_mw, t_odth{8,4} */\
+ .dramset1tmg14 = 0x000800A0, /* t_xsr, t_osco */ \
+ .dramset1tmg23 = 0x00000000, \
+ .dramset1tmg24 = 0x000F0F0F, \
+ .dramset1tmg25 = 0x00000000, \
+ .dramset1tmg30 = 0x00000000, \
+ /* \
+ * SDRAM initialization MR values — LPDDR5 mode registers. \
+ * TODO: encode MR1/MR2/MR11/MR13 for 1067 MHz RL/WL. \
+ */ \
+ .initmr0 = 0x00000000, \
+ .initmr1 = 0x00000000, \
+ .initmr2 = 0x00000000, \
+ .initmr3 = 0x00000000, \
+ /* \
+ * DFI timing — TRM reset values; tDFI_WRDATA and \
+ * tDFI_RDDATA_EN must be set per PHY latency for 1067 MHz. \
+ */ \
+ .dfitmg0 = 0x07020002, \
+ .dfitmg1 = 0x00000404, \
+ .dfitmg2 = 0x00000202, \
+ .dfitmg4 = 0x00000000, \
+ .dfitmg5 = 0x00000000, \
+ .dfilptmg0 = 0x00000000, \
+ .dfilptmg1 = 0x00000700, \
+ .dfiupdtmg0 = 0x00400003, \
+ .dfiupdtmg1 = 0x00010001, \
+ .dfimsgtmg0 = 0x00000004, \
+ /* \
+ * Refresh timing — TODO: t_rfc_min for LP5 8 Gbit die \
+ * (tRFCab ≈ 380 ns at 1067 MHz ≈ 406 cycles). \
+ */ \
+ .rfshset1tmg0 = 0x02100062, \
+ .rfshset1tmg1 = 0x0000008C, \
+ .rfshset1tmg2 = 0x8C8C0000, \
+ .rfshset1tmg4 = 0x00000000, \
+ /* ZQ timing — TRM reset values */ \
+ .zqset1tmg0 = 0x00400200, \
+ .zqset1tmg1 = 0x02000100, \
+ /* Scheduler / power — TRM reset values */ \
+ .perfhpr1 = 0x0F000001, \
+ .perflpr1 = 0x0F00007F, \
+ .perfwr1 = 0x0F00007F, \
+ .ranktmg0 = 0x00000606, \
+ .ranktmg1 = 0x00000F0F, \
+ .pwrtmg = 0x00400010, \
+}
+
+{
+ .ch = {
+ [0] = {
+ .cap_info = {
+ /*
+ * Typical 8 GB LPDDR5: 2 channels × 4 GB,
+ * each channel two x16 LP5 dies = x32 bus.
+ * 4 GB / 8 banks / 1024 cols / 4 B = 2^17 rows.
+ * Verify rank, row, col from actual chip datasheet.
+ */
+ .rank = 1,
+ .col = 10,
+ .bk = 3,
+ .bw = 2,
+ .dbw = 1,
+ .row_3_4 = 0,
+ .cs0_row = 17,
+ .cs1_row = 17,
+ .cs0_high16bit_row = 0,
+ .cs1_high16bit_row = 0,
+ .ddrconfig = 0,
+ },
+ },
+ [1] = {
+ .cap_info = {
+ .rank = 1,
+ .col = 10,
+ .bk = 3,
+ .bw = 2,
+ .dbw = 1,
+ .row_3_4 = 0,
+ .cs0_row = 17,
+ .cs1_row = 17,
+ .cs0_high16bit_row = 0,
+ .cs1_high16bit_row = 0,
+ .ddrconfig = 0,
+ },
+ },
+ },
+ .base = {
+ .ddr_freq = 2133, /* PHY 2x clock MHz; CK = 1067 MHz */
+ .dramtype = LPDDR5,
+ .num_channels = 2,
+ .stride = 0,
+ .odt = 1,
+ },
+ .freq = {
+ [0] = LP5_2133_FREQ_TMG,
+ [1] = LP5_2133_FREQ_TMG,
+ [2] = LP5_2133_FREQ_TMG,
+ [3] = LP5_2133_FREQ_TMG,
+ },
+ .ctl = {
+ /*
+ * MSTR0: LPDDR5 (BIT(6)), 1 rank (bits[25:24]=0x1),
+ * BL16 (bits[19:16]=0x8), full bus width (bits[13:12]=0x0).
+ * TRM Part 2 p.632 field descriptions.
+ */
+ .mstr0 = 0x01080040,
+ /* Remaining fields: TRM reset values (sdram_pctl_rk3576.h) */
+ .rankctl = 0x0000000F,
+ .dbictl = 0x00000001,
+ .odtmap = 0x00002211,
+ .inittmg0 = 0x0002004E,
+ .inittmg1 = 0x00000000,
+ .rfshmod0 = 0x00000000,
+ .sched0 = 0x8001201C,
+ .sched1 = 0x00002000,
+ .sched3 = 0x04040208,
+ .sched4 = 0x08400810,
+ .dfilpcfg0 = 0x00100000,
+ .dfiupd0 = 0x00008000,
+ .dfiphymstr = 0x80000001,
+ .zqctl0 = 0x00000000,
+ .zqctl1 = 0x00000000,
+ },
+},
+
+#undef LP5_2133_FREQ_TMG
--
2.45.1.windows.1
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