[PATCH v3 3/7] mtd: spi-nor-ids: Add support for GigaDevice GD25Q256

[Weijie Gao]

On Fri, 2026-05-22 at 07:55 +0000, Takahiro.Kuwano at infineon.com wrote:
> External email : Please do not click links or open attachments until
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> 
> 
> > GD25Q256 ia 256Mb flash device with Quad interface at max 80MHz
> > clock rate.
> 
> ia -> is
> 
> The datasheet says it's up-to 133MHz. If you tested at 80MHz, please
> mention
> that.
> 
> > This flash supports 2.7-3.6V voltage range.
> > 
> > Tested on MediaTek's filogic platform.
> > 
> > Link: 
> > https://urldefense.com/v3/__https://download.gigadevice.com/Datasheet/DS-00526-GD25Q256E-Rev1.3.pdf__;!!CTRNKA9wMg0ARbw!hEUSDGPOIwhKz5co5q62J5najY5WWOrcek_xV9OeEXby2PPbtBBWk4AwK4bms9x6tUKZNkKDkhOyzYQ6PfsifsLfjfXnqCQ$
> > 
> > Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
> 
> Please remove blank line between the tags.
> 
> > ---
> > v3: removed locking flags. updated commit message
> > v2: updated commit message
> > ---
> >  drivers/mtd/spi/spi-nor-ids.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-
> > nor-ids.c
> > index fcc546fb5ae..9271cefc759 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -147,6 +147,10 @@ const struct flash_info spi_nor_ids[] = {
> >                         SECT_4K | SPI_NOR_DUAL_READ |
> > SPI_NOR_QUAD_READ |
> >                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> >         },
> > +       {
> > +               INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
> > +                       SECT_4K | SPI_NOR_DUAL_READ |
> > SPI_NOR_QUAD_READ)
> > +       },
> 
> Same ID but different name entry below (I overlooked this in previous
> review).
> Both 'Q' and 'B' are available in GigaDevice website. What's the
> difference?

Hmm. I found that a bunch of chips share the same ID:
GD25Q256C/GD25Q256D/GD25Q256E/GD25Q257D
GD25B256D/GD25B256E/GD25B257D/GD25R256D

They both supports 4K sector and dual/quad read.
Differences I found are max speed, RPMC and DTR.

I'll remove this patch.

> 
> >         /* adding these 3V QSPI flash parts */
> >         {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512,  SECT_4K |
> >         SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> > SPI_NOR_4B_OPCODES)  },
> 
> Thanks,
> Takahiro
>