[PATCH v2 0/5] arm: aspeed: add initial AST2700 SoC support

[Ryan Chen]

> Subject: Re: [PATCH v2 0/5] arm: aspeed: add initial AST2700 SoC support
> 
> On Wed, May 20, 2026 at 04:24:47PM +0800, Ryan Chen wrote:
> 
> > AST2700 is the 8th generation of Integrated Remote Management
> > Processor introduced by ASPEED Technology Inc. It is a Board
> > Management Controller (BMC) SoC family with a dual-die architecture:
> > SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and
> > SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock
> > dividers and reset domains.
> >
> > Signed-off-by: Ryan Chen <ryan_chen at aspeedtech.com>
> > ---
> > Changes in v2:
> >   * v1 only have clk driver, v2 apply full AST2700 platform and
> >     reset, clk, ram driver.
> >   * Move scu_ast2700.h from the clk patch into the mach-aspeed
> >     patch so the SoC header is provided alongside the SoC code
> >     that consumes it.
> >   * Link to v1:
> > https://lore.kernel.org/r/20260508-ast2700_clk-v1-1-2797a626a238@aspee
> > dtech.com
> 
> Somewhere in this series, a MAINTAINERS entry should be updated with:
> N: ast2700
> As well, thanks!
> 
> --
Hello Tom,
Thanks.
Will added N: ast2700 to the ARM ASPEED MAINTAINERS.

Will send v3 shortly.