[PATCH] clk: qcom: sa8775p: Add SDCC1 clock support with frequency table

[Casey Connolly]

On 26/05/2026 10:58, Balaji Selvanathan wrote:
> Add support for SDCC1 (eMMC) clock on SA8775P platform.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan at oss.qualcomm.com>

Reviewed-by: Casey Connolly <casey.connolly at linaro.org>

> ---
>  drivers/clk/qcom/clock-sa8775p.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
> index 4957abf6f58..0ec4ad041c6 100644
> --- a/drivers/clk/qcom/clock-sa8775p.c
> +++ b/drivers/clk/qcom/clock-sa8775p.c
> @@ -44,6 +44,22 @@
>  
>  #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25)
>  
> +#define SDCC1_APPS_CLK_CMD_RCGR			0x20014
> +
> +/* SDCC1 APPS clock frequency table */
> +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
> +	F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
> +	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
> +	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +	F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 1, 3),
> +	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> +	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
> +	F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
> +	F(192000000, CFG_CLK_SRC_GPLL9, 4, 0, 0),
> +	F(384000000, CFG_CLK_SRC_GPLL9, 2, 0, 0),
> +	{ }
> +};
> +
>  static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
>  {
>  	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -63,6 +79,11 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
>  				     5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
>  		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
>  		return rate;
> +	case GCC_SDCC1_APPS_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +		return freq->freq;
>  	default:
>  		return 0;
>  	}
> @@ -106,6 +127,10 @@ static const struct gate_clk sa8775p_clks[] = {
>  
>  	/* QUP Wrapper 3 clocks */
>  	GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT),
> +
> +	/* SDCC1 clocks */
> +	GATE_CLK(GCC_SDCC1_AHB_CLK, 0x2000c, 1),
> +	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x20004, 1),
>  };
>  
>  static int sa8775p_enable(struct clk *clk)
> 
> ---
> base-commit: 76d62273bc8a5dc126ed79ed0fb65e5a97359577
> change-id: 20260526-mmc-328c4d2c9055
> 
> Best regards,

-- 
// Casey (she/her)