[PATCH RFC 02/18] clk: rockchip: rk3568: Fix probe with OF_PLATDATA enabled

[Pavel Golikov]

Hi Jonas,

On Tue, May 26, 2026 at 10:17:16AM +0200, Jonas Karlman wrote:
> Hi Pavel,
> 
> On 5/24/2026 9:39 PM, Pavel Golikov wrote:
> > Hi Jonas,
> > 
> > On Sun, May 24, 2026 at 08:42:33PM +0200, Jonas Karlman wrote:
> >> Hi Pavel,
> >>
> >> On 5/17/2026 9:24 PM, Pavel Golikov wrote:
> >>> Properly initialize cru address space reference when CONFIG_OF_PLATDATA
> >>> is enabled.
> >>
> >> Do we have to use OF_PLATDATA for TPL to fit into SRAM?
> > 
> > DRAM driver is heavily based on one for rv1126. rv1126 utilizes OF_PLATDATA,
> > even though it is 32 bit (with the same amount of SRAM), and 32 bit TPL should
> > be even smaller.
> 
> None of the existing Rockchip TPL implementation is very optimized and
> likely not a good candidate on how optimized DRAM init can be handled :-)
> 
> >> Also, why do we need CLK driver in TPL? Based on small glance at the
> >> code it looks like the DPLL was handled by the RAM driver itself.
> > 
> > I'm getting
> > 
> > aarch64-linux-gnu-ld: arch/arm/mach-rockchip/rk3568/clk_rk3568.o: in function `rockchip_get_clk':
> > <...>/build-tpl/../arch/arm/mach-rockchip/rk3568/clk_rk3568.c:14: undefined reference to `_u_boot_list_2_driver_2_rockchip_rk3568_cru'
> > aarch64-linux-gnu-ld: <...>/build-tpl/../arch/arm/mach-rockchip/rk3568/clk_rk3568.c:14: undefined reference to `_u_boot_list_2_driver_2_rockchip_rk3568_cru'
> > 
> > when trying to build TPL without CLK (both with OF_PLATDATA and OF_REAL).
> > rockchip_get_clk is needed by sysreset_rockchip, which, in turn, is always
> > built for ARCH_ROCKCHIP (sorry).
> 
> Correct, as I mentioned, there are dependency issues that needs to be
> resolved, the question remains, does the DRAM init code need to
> initialize any clocks that is currently handled in the clock driver?

No, it does not.
 
> Or could macros from cru_rk3568.h be used directly in DRAM init code
> to save on size?
> 
> Anyway, I have some work-in-progress code [1] that cleanup some of these
> dependency issues and should allow for a very light TPL.
> 
>   make generic-rk3568_defconfig rockchip-tpl-lpddr4.config
> 
> With that I get a ~2 KiB TPL that could be used as a starting ground
> for a size optimized DRAM init.

Did a quick rebase on top of your branch here [1]. It works without TPL_DM, but
requires CFG_SYS_NS16550_CLK and CFG_SYS_NS16550_COM1 definitions to make it
all buildable.

46184 vs 37288 bytes for TPL, and no malloc in the image. Impressive.

But still board_init_f_alloc_reserve(0xfdcd8000). I also wonder why we move
stack pointer on TPL start, instead of using the stack provided by bootrom.
I suspect that 0xfdcc0600 - 0xfdcc1000 is a bootrom stack region.

I also noticed that debug_uart_init() is called twice. Once in
crt0.S/crt0_64.S, and once in board_init_f. Is this behaviour intended?

> Implement board_debug_uart_init(), sdram_init() and the missing RK3568
> specific TPL Kconfig options, i.e. TPL_TEXT_BASE etc. and hopefully that
> should be enough for a size optimized DRAM init.
> 
> [1] https://source.denx.de/u-boot/contributors/kwiboo/u-boot/-/commits/ci
> 
> I will rework some of those patches and send to list later this week.
> 
> Regards,
> Jonas
> 
> > 
> > We could actually delegate DPLL to CLK, but there is no API to configure spread
> > spectrum (although it is disabled by default in loader_params). I also have no
> > idea of how MSCH clock tree looks like.
> > 
> > Regards,
> > Pavel 
> 

[1] https://github.com/Paullo612/u-boot/tree/ci-rk3568-raminit-rfc-v2

Regards,
Pavel