[PATCH v2 3/6] misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver

[Simon Glass]

Hi Aswin,

On 2026-02-13T11:27:11, Aswin Murugan <aswin.murugan at oss.qualcomm.com> wrote:
> misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver
>
> Qualcomm PMICs include SDAM (Shared Direct Access Memory) regions which
> are used to store persistent data like reboot reasons that must survive
> across reboots.
>
> Without this driver, U-Boot cannot access PMIC storage, preventing
> reboot-to-bootloader functionality and other features that rely on
> persistent state.
>
> Add qcom-spmi-sdam driver that:
> - Probes SDAM regions from device tree compatible 'qcom,spmi-sdam'
> - Implements NVMEM provider interface for standard cell-based access
> - Uses SPMI register read/write operations for data access
>
> This enables reboot-mode and other subsystems to access PMIC storage
> through standard NVMEM APIs.
>
> Signed-off-by: Aswin Murugan <aswin.murugan at oss.qualcomm.com>
>
> drivers/misc/Kconfig          |   8 ++
>  drivers/misc/Makefile         |   1 +
>  drivers/misc/qcom-spmi-sdam.c | 200 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 209 insertions(+)

> diff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c
> @@ -0,0 +1,200 @@
> +struct qcom_sdam_priv {
> +     u32 base;
> +     u32 size;
> +     u32 pmic_usid;
> +     struct udevice *spmi_dev;
> +};

For base can you use ulong or fdt_addr_t ? The u32 will truncate the
FDT_ADDR_T_NONE check below.

> diff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c
> @@ -0,0 +1,200 @@
> +     *spmi_dev = pmic_dev->parent;
> +     if (!*spmi_dev || (*spmi_dev)->uclass->uc_drv->id != UCLASS_SPMI) {
> +             dev_err(dev, "Could not find SPMI controller\n");
> +             return -ENODEV;
> +     }

Please use device_get_uclass_id(*spmi_dev) rather than reaching into
uclass/uc_drv internals.

> diff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c
> @@ -0,0 +1,200 @@
> +/**
> + * qcom_sdam_probe() - Probe SDAM device and register as NVMEM provider
> + * @dev: SDAM device
> + *
> + * Handles both real SDAM blocks and virtual NVMEM under PON blocks.
> + * For virtual NVMEM, adds the parent PON base address to the offset.
> + *
> + * Return: 0 on success, negative error code on failure
> + */
> +static int qcom_sdam_probe(struct udevice *dev)

The kerneldoc is misleading. Nothing here registers an NVMEM provider
- the NVMEM core picks the device up via UCLASS_MISC. And there's no
code that adds the parent PON base address to the offset; priv->base
is whatever dev_read_addr() returns. Please trim to match the code.

> diff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c
> @@ -0,0 +1,200 @@
> +     priv->size = dev_read_u32_default(dev, 'qcom,sdam-size', SDAM_SIZE);

Can you check the binding for qcom,spmi-sdam ? I don't see
'qcom,sdam-size' - so instead you should use
dev_read_addr_size_index() so size comes from 'reg'

> diff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c
> @@ -0,0 +1,200 @@
> +     for (size_t i = 0; i < size; i++) {
> +             u32 reg = priv->base + offset + i;
> +
> +             ret = spmi_reg_read(priv->spmi_dev, priv->pmic_usid,
> +                                 (reg & PID_MASK) >> PID_SHIFT,
> +                                 reg & REG_MASK);

For later consideration: if reading a lot of bytes, can we use a burst read?

Declarations should be at the top of the function...also best to use
int for the loop var, to match 'size'.

> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> @@ -93,6 +93,14 @@ config QCOM_GENI
> +config QCOM_SPMI_SDAM
> +     bool "Qualcomm SPMI SDAM NVMEM driver"
> +     depends on MISC && NVMEM && SPMI
> +     help
> +       Enable support for Qualcomm SPMI SDAM (Shared Direct Access Memory) blocks
> +       as NVMEM providers. This driver support accessing SDAM blocks in PMICs
> +       for reboot reason functionality and other NVMEM use cases.

'driver support' should be 'driver supports'

Check the help text fits in 80 columns.

With these:
Reviewed-by: Simon Glass <sjg at chromium.org>

Regards,
Simon