[PATCH v1] serial: lpuart: Fix RX FIFO Enable bitmask

[Emanuele Ghidoli]

From: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>

The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is
bit 3 on all supported architectures. The define has been wrong since
it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA
is read-only-as-zero, so the bug went unnoticed.

NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based
selection.

Link: https://github.com/nxp-imx/uboot-imx/commit/9498bcc514737269bb0ca436f775460741ab8199
Link: https://lore.kernel.org/u-boot/dc163ea7-9063-4dfb-a39a-e643c0bcccf1@oss.nxp.com/
Fixes: 6209e14cb026 ("serial: lpuart: add 32-bit registers lpuart support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>
---
 drivers/serial/serial_lpuart.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 9fdb6503085d..3f5fadfc80a5 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -53,11 +53,7 @@
 #define FIFO_RXSIZE_MASK	0x7
 #define FIFO_RXSIZE_OFF	0
 #define FIFO_TXFE		0x80
-#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
 #define FIFO_RXFE		0x08
-#else
-#define FIFO_RXFE		0x40
-#endif
 
 #define WATER_TXWATER_OFF	0
 #define WATER_RXWATER_OFF	16
-- 
2.43.0