[PATCH v1] serial: lpuart: Fix RX FIFO Enable bitmask

[Sébastien Szymanski]

On 5/28/26 3:49 PM, Emanuele Ghidoli wrote:
> From: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>
> 
> The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is
> bit 3 on all supported architectures. The define has been wrong since
> it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA
> is read-only-as-zero, so the bug went unnoticed.
> 
> NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based
> selection.
> 
> Link: https://github.com/nxp-imx/uboot-imx/commit/9498bcc514737269bb0ca436f775460741ab8199
> Link: https://lore.kernel.org/u-boot/dc163ea7-9063-4dfb-a39a-e643c0bcccf1@oss.nxp.com/
> Fixes: 6209e14cb026 ("serial: lpuart: add 32-bit registers lpuart support")
> Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>

Reviewed-by: Sébastien Szymanski <sebastien.szymanski at armadeus.com>

-- 
Sébastien Szymanski, Armadeus Systems
Software engineer