[PATCH] arm: imx9: Fix broken formatting
Marek Vasut
marex at nabladev.com
Sat May 30 12:47:53 CEST 2026
Fix ad-hoc tabs and spaces use, convert to tabs. Drop bogus duplicate
asterisk from non-kerneldoc code comments. No functional change.
Signed-off-by: Marek Vasut <marex at nabladev.com>
---
Cc: "NXP i.MX U-Boot Team" <uboot-imx at nxp.com>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Simona Toaca <simona.toaca at nxp.com>
Cc: Stefano Babic <sbabic at nabladev.com>
Cc: Tom Rini <trini at konsulko.com>
Cc: Viorel Suman <viorel.suman at nxp.com>
Cc: Ye Li <ye.li at nxp.com>
Cc: u-boot at lists.denx.de
---
arch/arm/include/asm/arch-imx9/ddr.h | 30 ++++++++++++++--------------
arch/arm/mach-imx/cmd_qb.c | 2 +-
arch/arm/mach-imx/imx9/qb.c | 24 +++++++++++-----------
3 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index bba12369f06..b0f90b53f64 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -13,21 +13,21 @@
#define DDR_PHY_BASE 0x4E100000
#define DDRMIX_BLK_CTRL_BASE 0x4E010000
-#define REG_DDR_SDRAM_MD_CNTL (DDR_CTL_BASE + 0x120)
-#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0)
-#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8)
+#define REG_DDR_SDRAM_MD_CNTL (DDR_CTL_BASE + 0x120)
+#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0)
+#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8)
#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
-#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
+#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
-#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
+#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
-#define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE + 0x260)
-#define REG_DDR_SDRAM_CFG_4 (DDR_CTL_BASE + 0x264)
-#define REG_DDR_SDRAM_MD_CNTL_2 (DDR_CTL_BASE + 0x270)
-#define REG_DDR_SDRAM_MPR4 (DDR_CTL_BASE + 0x28C)
-#define REG_DDR_SDRAM_MPR5 (DDR_CTL_BASE + 0x290)
+#define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE + 0x260)
+#define REG_DDR_SDRAM_CFG_4 (DDR_CTL_BASE + 0x264)
+#define REG_DDR_SDRAM_MD_CNTL_2 (DDR_CTL_BASE + 0x270)
+#define REG_DDR_SDRAM_MPR4 (DDR_CTL_BASE + 0x28C)
+#define REG_DDR_SDRAM_MPR5 (DDR_CTL_BASE + 0x290)
-#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000)
+#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000)
#define SRC_BASE_ADDR (0x44460000)
#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
@@ -107,13 +107,13 @@ extern struct dram_timing_info dram_timing;
#define DDRPHY_QB_PSTATES 0
#define DDRPHY_QB_PST_SIZE (DDRPHY_QB_PSTATES * 4 * 1024)
-/**
+/*
* This structure needs to be aligned with the one in OEI.
*/
struct ddrphy_qb_state {
- u32 crc; /* Used for ensuring integrity in DRAM */
-#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */
- u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */
+ u32 crc; /* Used for ensuring integrity in DRAM */
+#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */
+ u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */
u8 trained_vrefca_a0;
u8 trained_vrefca_a1;
u8 trained_vrefca_b0;
diff --git a/arch/arm/mach-imx/cmd_qb.c b/arch/arm/mach-imx/cmd_qb.c
index 633d83d3abd..a6b654d342f 100644
--- a/arch/arm/mach-imx/cmd_qb.c
+++ b/arch/arm/mach-imx/cmd_qb.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
-/**
+/*
* Copyright 2024-2026 NXP
*/
#include <command.h>
diff --git a/arch/arm/mach-imx/imx9/qb.c b/arch/arm/mach-imx/imx9/qb.c
index 1a0a12de3d4..ac4d10b5885 100644
--- a/arch/arm/mach-imx/imx9/qb.c
+++ b/arch/arm/mach-imx/imx9/qb.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
-/**
+/*
* Copyright 2024-2026 NXP
*/
#include <dm/device-internal.h>
@@ -17,15 +17,15 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sys_proto.h>
-#define QB_STATE_LOAD_SIZE SZ_64K
+#define QB_STATE_LOAD_SIZE SZ_64K
-#define BLK_DEV 0
-#define SPI_DEV 1
+#define BLK_DEV 0
+#define SPI_DEV 1
-#define IMG_FLAGS_IMG_TYPE_MASK 0xF
-#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x))
+#define IMG_FLAGS_IMG_TYPE_MASK 0xF
+#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x))
-#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */
+#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */
static const struct {
const char *ifname;
@@ -33,7 +33,7 @@ static const struct {
} imx_boot_devs[] = {
[BOOT_DEVICE_MMC1] = { "mmc", "0" },
[BOOT_DEVICE_MMC2] = { "mmc", "1" },
- [BOOT_DEVICE_SPI] = { "spi", "" },
+ [BOOT_DEVICE_SPI] = { "spi", "" },
};
static int imx_qb_get_board_boot_device(void)
@@ -77,7 +77,7 @@ bool imx_qb_check(void)
struct ddrphy_qb_state *qb_state;
u32 size, crc;
- /**
+ /*
* Ensure CRC is not empty, the reason is that
* the data is invalidated after first save run
* or after it is overwritten.
@@ -105,7 +105,7 @@ static int imx_qb_get_blk_boot_part(const char * const ifname,
if (!IS_ENABLED(CONFIG_XPL_BUILD))
return blk_get_device_part_str(ifname, dev, bdesc, &info, 1);
- /**
+ /*
* SPL does not have access to part_get_info,
* so get the partition manually. Currently only
* supporting MMC devices.
@@ -364,7 +364,7 @@ int imx_qb(const char *ifname, const char *dev, bool save)
ret = 0;
- /* Try to use boot device */
+ /* Try to use boot device */
if (!strcmp(ifname, "auto"))
ret = imx_qb_get_boot_dev_str(&ifname, &dev);
@@ -385,7 +385,7 @@ int imx_qb(const char *ifname, const char *dev, bool save)
if (!save)
return 0;
- /**
+ /*
* invalidate qb_state mem so that at next boot
* the check function will fail and save won't happen
*/
--
2.53.0
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