diff -ruNb u-boot-original/cpu/mpc8xx/fec.c u-boot-fec/cpu/mpc8xx/fec.c
--- u-boot-original/cpu/mpc8xx/fec.c	2004-03-30 14:37:28.695926464 +0300
+++ u-boot-fec/cpu/mpc8xx/fec.c	2004-03-30 16:39:29.881937016 +0300
@@ -29,13 +29,71 @@
 
 #undef	ET_DEBUG
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && \
+	(defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
 
-#ifdef CFG_DISCOVER_PHY
+/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
+#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) 
+#define CONFIG_ETHER_ON_FEC1 1
+#endif
+
+/* define WANT_MII when MII support is required */
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
+#define WANT_MII
+#else
+#undef WANT_MII
+#endif
+
+#if defined(WANT_MII)
 #include <miiphy.h>
-static void mii_discover_phy(void);
 #endif
 
+#if defined(CONFIG_RMII) && !defined(WANT_MII)
+#error RMII support is unusable without a working PHY.
+#endif
+
+#ifdef CFG_DISCOVER_PHY
+static int mii_discover_phy(struct eth_device *dev);
+#endif
+
+static struct ether_fcc_info_s
+{
+	int ether_index;
+	int fecp_offset;
+	int bd_offset;
+	int phy_addr;
+	int actual_phy_addr;
+}
+	ether_fcc_info[] = {
+#if defined(CONFIG_ETHER_ON_FEC1)
+	{
+		0,
+		offsetof(immap_t, im_cpm.cp_fec1),
+		CPM_FEC_BASE,
+#if defined(CONFIG_FEC1_PHY)
+		CONFIG_FEC1_PHY,
+#else
+		-1,	/* discover */
+#endif
+		-1,
+
+	},
+#endif
+#if defined(CONFIG_ETHER_ON_FEC2)
+	{
+		1,
+		offsetof(immap_t, im_cpm.cp_fec2),
+		CPM_FEC_BASE + 0x50,
+#if defined(CONFIG_FEC2_PHY)
+		CONFIG_FEC2_PHY,
+#else
+		-1,
+#endif
+		-1,
+	},
+#endif
+};
+
 /* Ethernet Transmit and Receive Buffers */
 #define DBUF_LENGTH  1520
 
@@ -47,8 +105,11 @@
 #define PKT_MINBUF_SIZE		64
 #define PKT_MAXBLR_SIZE		1520
 
-
-static char txbuf[DBUF_LENGTH];
+#ifdef __GNUC__
+static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
+#else
+#error txbuf must be aligned.
+#endif
 
 static uint rxIdx;	/* index of the current RX buffer */
 static uint txIdx;	/* index of the current TX buffer */
@@ -74,28 +135,47 @@
 int fec_initialize(bd_t *bis)
 {
 	struct eth_device* dev;
+	struct ether_fcc_info_s *efis;
+	int             i;
 
-	dev = (struct eth_device*) malloc(sizeof *dev);
-	memset(dev, 0, sizeof *dev);
+	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
 
+		dev = malloc(sizeof(*dev));
+		if (dev == NULL)
+			hang();
+
+		memset(dev, 0, sizeof(*dev));
+
+		/* for FEC1 make sure that the name of the interface is the same
+		   as the old one for compatibility reasons */
+		if (i == 0)
 	sprintf(dev->name, "FEC ETHERNET");
-	dev->iobase = 0;
-	dev->priv   = 0;
+		else
+			sprintf(dev->name, "FEC%d ETHERNET", ether_fcc_info[i].ether_index + 1);
+
+		efis = &ether_fcc_info[i];
+
+		/*
+		 * reset actual phy addr 
+		 */
+		efis->actual_phy_addr = -1;
+
+		dev->priv = efis;
 	dev->init   = fec_init;
 	dev->halt   = fec_halt;
 	dev->send   = fec_send;
 	dev->recv   = fec_recv;
 
 	eth_register(dev);
-
+	}
 	return 1;
 }
 
 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
 {
 	int j, rc;
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
+	struct ether_fcc_info_s *efis = dev->priv;
+	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
 
 	/* section 16.9.23.3
 	 * Wait for ready
@@ -144,9 +224,9 @@
 
 static int fec_recv(struct eth_device* dev)
 {
+	struct ether_fcc_info_s *efis = dev->priv;
+	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
 	int length;
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
 
    for (;;) {
 	/* section 16.9.23.2 */
@@ -163,8 +243,19 @@
 		__FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
 #endif
 	} else {
-		/* Pass the packet up to the protocol layers. */
-		NetReceive(NetRxPackets[rxIdx], length - 4);
+			volatile uchar *rx = NetRxPackets[rxIdx];
+
+			length -= 4;
+
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+			if ((rx[0] & 1) != 0 && memcmp((uchar *)rx, NetBcastAddr, 6) != 0 && memcmp((uchar *)rx, NetCDPAddr, 6) != 0)
+				rx = NULL;
+#endif
+			/*
+			 * Pass the packet up to the protocol layers. 
+			 */
+			if (rx != NULL)
+				NetReceive(rx, length);
 	}
 
 	/* Give the buffer back to the FEC. */
@@ -210,13 +301,228 @@
 
 #define	FEC_RESET_DELAY		50
 
-static int fec_init(struct eth_device* dev, bd_t * bd)
+#if defined(CONFIG_RMII)
+
+static inline void fec_10Mbps(struct eth_device *dev)
 {
+	struct ether_fcc_info_s *efis = dev->priv;
+	int fecidx = efis->ether_index;
 
-	int i;
+	if ((unsigned int)fecidx >= 2)
+		hang();
+
+	if (fecidx == 0)
+		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |=  0x0000010;
+	else
+		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |=  0x0000008;
+}
+
+static inline void fec_100Mbps(struct eth_device *dev)
+{
+	struct ether_fcc_info_s *efis = dev->priv;
+	int fecidx = efis->ether_index;
+
+	if ((unsigned int)fecidx >= 2)
+		hang();
+
+	if (fecidx == 0)
+		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~0x0000010;
+	else
+		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~0x0000008;
+}
+
+#endif
+
+static inline void fec_full_duplex(struct eth_device *dev)
+{
+	struct ether_fcc_info_s *efis = dev->priv;
+	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+
+	fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
+	fecp->fec_x_cntrl |=  FEC_TCNTRL_FDEN;	/* FD enable */
+}
+
+static inline void fec_half_duplex(struct eth_device *dev)
+{
+	struct ether_fcc_info_s *efis = dev->priv;
+	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+
+	fecp->fec_r_cntrl |=  FEC_RCNTRL_DRT;
+	fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN;	/* FD disable */
+}
+
+static void fec_pin_init(int fecidx)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t           *bd = gd->bd;
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
-	volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
+	volatile fec_t *fecp;
+
+	/*
+	 * only two FECs please 
+	 */
+	if ((unsigned int)fecidx >= 2)
+		hang();
+
+	if (fecidx == 0)
+		fecp = &immr->im_cpm.cp_fec1;
+	else
+		fecp = &immr->im_cpm.cp_fec2;
+
+	/*
+	 * Set MII speed to 2.5 MHz or slightly below.
+	 * * According to the MPC860T (Rev. D) Fast ethernet controller user
+	 * * manual (6.2.14),
+	 * * the MII management interface clock must be less than or equal
+	 * * to 2.5 MHz.
+	 * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
+	 * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
+	 */
+	fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
+
+#if defined(CONFIG_DUET) && defined(WANT_MII)
+	/* use MDC for MII */
+	immr->im_ioport.iop_pdpar |=  0x0080;
+	immr->im_ioport.iop_pddir &= ~0x0080;
+#endif
+
+	if (fecidx == 0) {
+#if defined(CONFIG_ETHER_ON_FEC1)
+
+#if defined(CONFIG_DUET)	/* MPC87x/88x have got 2 FECs and different pinout */
+
+#if !defined(CONFIG_RMII)
+
+		immr->im_ioport.iop_papar |=  0xf830;
+		immr->im_ioport.iop_padir |=  0x0830;
+		immr->im_ioport.iop_padir &= ~0xf000;
+
+		immr->im_cpm.cp_pbpar     |=  0x00001001;
+		immr->im_cpm.cp_pbdir     &= ~0x00001001;
+
+		immr->im_ioport.iop_pcpar |=  0x000c;
+		immr->im_ioport.iop_pcdir &= ~0x000c;
+
+		immr->im_cpm.cp_pepar     |=  0x00000003;
+		immr->im_cpm.cp_pedir     |=  0x00000003;
+		immr->im_cpm.cp_peso      &= ~0x00000003;
+
+		immr->im_cpm.cp_cptr      &= ~0x00000100;
+
+#else
+
+#if !defined(CONFIG_FEC1_PHY_NORXERR)
+		immr->im_ioport.iop_papar |=  0x1000;
+		immr->im_ioport.iop_padir &= ~0x1000;
+#endif
+		immr->im_ioport.iop_papar |=  0xe810;
+		immr->im_ioport.iop_padir |=  0x0810;
+		immr->im_ioport.iop_padir &= ~0xe000;
+
+		immr->im_cpm.cp_pbpar     |=  0x00000001;
+		immr->im_cpm.cp_pbdir     &= ~0x00000001;
+
+		immr->im_cpm.cp_cptr      |=  0x00000100;
+		immr->im_cpm.cp_cptr      &= ~0x00000050;
+
+#endif /* !CONFIG_RMII */
+
+#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
+		/*
+		 * Configure all of port D for MII.
+		 */
+		immr->im_ioport.iop_pdpar = 0x1fff;
+
+		/*
+		 * Bits moved from Rev. D onward 
+		 */
+		if ((get_immr(0) & 0xffff) < 0x0501)
+			immr->im_ioport.iop_pddir = 0x1c58;	/* Pre rev. D */
+		else
+			immr->im_ioport.iop_pddir = 0x1fff;	/* Rev. D and later */
+#else
+		/*
+		 * Configure port A for MII.
+		 */
+
+#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
+
+		/*
+		 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
+		 * * of CPU, so for this board we need to configure Utopia and
+		 * * enable PD8 to MII-MDC function 
+		 */
+		immr->im_ioport.iop_pdpar |= 0x4080;
+#endif
+
+		/*
+		 * Has Utopia been configured? 
+		 */
+		if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
+			/*
+			 * YES - Use MUXED mode for UTOPIA bus.
+			 * This frees Port A for use by MII (see 862UM table 41-6).
+			 */
+			immr->im_ioport.utmode &= ~0x80;
+		} else {
+			/*
+			 * NO - set SPLIT mode for UTOPIA bus.
+			 *
+			 * This doesn't really effect UTOPIA (which isn't
+			 * enabled anyway) but just tells the 862
+			 * to use port A for MII (see 862UM table 41-6).
+			 */
+			immr->im_ioport.utmode |= 0x80;
+		}
+#endif				/* !defined(CONFIG_ICU862) */
+
+#endif	/* CONFIG_ETHER_ON_FEC1 */
+	} else if (fecidx == 1) {
+
+#if defined(CONFIG_ETHER_ON_FEC2)
+
+#if defined(CONFIG_DUET)	/* MPC87x/88x have got 2 FECs and different pinout */
+
+#if !defined(CONFIG_RMII)
+
+#warning this configuration is not tested; please report if it works
+		immr->im_cpm.cp_pepar     |=  0x0003fffc;
+		immr->im_cpm.cp_pedir     |=  0x0003fffc;
+		immr->im_cpm.cp_peso      &= ~0x000087fc;
+		immr->im_cpm.cp_peso      |=  0x00037800;
+
+		immr->im_cpm.cp_cptr      &= ~0x00000080;
+#else
+
+#if !defined(CONFIG_FEC2_PHY_NORXERR)
+		immr->im_cpm.cp_pepar     |=  0x00000010;
+		immr->im_cpm.cp_pedir     |=  0x00000010;
+		immr->im_cpm.cp_peso      &= ~0x00000010;
+#endif
+		immr->im_cpm.cp_pepar     |=  0x00039620;
+		immr->im_cpm.cp_pedir     |=  0x00039620;
+		immr->im_cpm.cp_peso      |=  0x00031000;
+		immr->im_cpm.cp_peso      &= ~0x00008620;
+
+		immr->im_cpm.cp_cptr      |=  0x00000080;
+		immr->im_cpm.cp_cptr      &= ~0x00000028;
+#endif /* CONFIG_RMII */
+
+#endif /* CONFIG_DUET */
+
+#endif /* CONFIG_ETHER_ON_FEC2 */
+
+	}
+}
+
+static int fec_init(struct eth_device *dev, bd_t * bd)
+{
+	struct ether_fcc_info_s *efis = dev->priv;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+	int             i;
 
+	if (efis->ether_index == 0) {
 #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
 #if defined(CONFIG_DUET_ADS)
 	*(vu_char *)BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
@@ -238,6 +544,8 @@
 	}
 #endif /* CONFIG_DUET_ADS */
 #endif /* CONFIG_FADS */
+	}
+
 	/* Whack a reset.
 	 * A delay is required between a reset of the FEC block and
 	 * initialization of other FEC registers because the reset takes
@@ -274,10 +582,18 @@
 	fecp->fec_addr_high  =	(ea[4] <<  8) | (ea[5]	    ) ;
 #undef ea
 
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+	/*
+	 * Turn on multicast address hash table
+	 */
+	fecp->fec_hash_table_high = 0xffffffff;
+	fecp->fec_hash_table_low = 0xffffffff;
+#else
 	/* Clear multicast address hash table
 	 */
 	fecp->fec_hash_table_high = 0;
 	fecp->fec_hash_table_low  = 0;
+#endif
 
 	/* Set maximum receive buffer size.
 	 */
@@ -343,82 +659,53 @@
 	 */
 	fecp->fec_fun_code = 0x78000000;
 
-	/* Set MII speed to 2.5 MHz or slightly below.
-	 * According to the MPC860T (Rev. D) Fast ethernet controller user
-	 * manual (6.2.14),
-	 * the MII management interface clock must be less than or equal
-	 * to 2.5 MHz.
-	 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
-	 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
-	 */
-	fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
-
-#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
-	immr->im_ioport.iop_papar |=  0xf830;
-	immr->im_ioport.iop_padir |=  0x0830;
-	immr->im_ioport.iop_padir &= ~0xf000;
-	immr->im_cpm.cp_pbpar     |=  0x00001001;
-	immr->im_cpm.cp_pbdir     &= ~0x00001001;
-	immr->im_ioport.iop_pcpar |=  0x000c;
-	immr->im_ioport.iop_pcdir &= ~0x000c;
-	immr->im_ioport.iop_pdpar |=  0x0080;
-	immr->im_ioport.iop_pddir &= ~0x0080;
-	immr->im_cpm.cp_pepar     |=  0x00000003;
-	immr->im_cpm.cp_pedir     |=  0x00000003;
-	immr->im_cpm.cp_peso      &= ~0x00000003;
-#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
-	/* Configure all of port D for MII.
-	 */
-	immr->im_ioport.iop_pdpar = 0x1fff;
-
-	/* Bits moved from Rev. D onward */
-	if ((get_immr (0) & 0xffff) < 0x0501) {
-		immr->im_ioport.iop_pddir = 0x1c58;	/* Pre rev. D */
-	} else {
-		immr->im_ioport.iop_pddir = 0x1fff;	/* Rev. D and later */
-	}
-#else
-	/* Configure port A for MII.
+	/*
+	 * Setup the pin configuration of the FEC
 	*/
+	fec_pin_init(efis->ether_index);
 
-#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
-
-	/* On the ICU862 board the MII-MDC pin is routed to PD8 pin
-	 * of CPU, so for this board we need to configure Utopia and
-	 * enable PD8 to MII-MDC function */
-	immr->im_ioport.iop_pdpar |= 0x4080;
-#endif
+	rxIdx = 0;
+	txIdx = 0;
 
-	/* Has Utopia been configured? */
-	if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
 		/*
-		 * YES - Use MUXED mode for UTOPIA bus.
-		 * This frees Port A for use by MII (see 862UM table 41-6).
+	 * Now enable the transmit and receive processing
 		 */
-		immr->im_ioport.utmode &= ~0x80;
-	} else {
+	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+
+	if (efis->phy_addr == -1) {
+#ifdef CFG_DISCOVER_PHY
 		/*
-		 * NO - set SPLIT mode for UTOPIA bus.
-		 *
-		 * This doesn't really effect UTOPIA (which isn't
-		 * enabled anyway) but just tells the 862
-		 * to use port A for MII (see 862UM table 41-6).
+		 * wait for the PHY to wake up after reset 
 		 */
-		immr->im_ioport.utmode |= 0x80;
+		efis->actual_phy_addr = mii_discover_phy(dev);
+#else
+		efis->actual_phy_addr = -1;
+#endif
+		if (efis->actual_phy_addr == -1) {
+			printf("Unable to discover phy!\n");
+			return 0;
 	}
-#endif	/* !defined(CONFIG_ICU862) */
-
-	rxIdx = 0;
-	txIdx = 0;
+	} else
+		efis->actual_phy_addr = efis->phy_addr;
 
-	/* Now enable the transmit and receive processing
+#if defined(CONFIG_MII) && defined(CONFIG_RMII)
+	/*
+	 * adapt the RMII speed to the speed of the phy 
 	 */
-	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+	if (miiphy_speed(efis->actual_phy_addr) == _100BASET)
+		fec_100Mbps(dev);
+	else
+		fec_10Mbps(dev);
+#endif
 
-#ifdef CFG_DISCOVER_PHY
-	/* wait for the PHY to wake up after reset
+#if defined(CONFIG_MII)
+	/*
+	 * adapt to the half/full speed settings 
 	 */
-	mii_discover_phy();
+	if (miiphy_duplex(efis->actual_phy_addr) == FULL)
+		fec_full_duplex(dev);
+	else
+		fec_half_duplex(dev);
 #endif
 
 	/* And last, try to fill Rx Buffer Descriptors */
@@ -444,10 +731,7 @@
 }
 #endif
 
-#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
-
-static	int	phyaddr = -1;	/* didn't find a PHY yet */
-static	uint	phytype;
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
 
 /* Make MII read/write commands for the FEC.
 */
@@ -508,12 +792,13 @@
 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
 
 #if defined(CFG_DISCOVER_PHY)
-static void
-mii_discover_phy(void)
+static int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
 	uint phyno;
 	int  pass;
+	uint phytype;
+	int phyaddr;
 
 	phyaddr = -1;	/* didn't find a PHY yet */
 	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
@@ -571,10 +856,11 @@
 	if (phyaddr < 0) {
 		printf("No PHY device found.\n");
 	}
+	return phyaddr;
 }
 #endif	/* CFG_DISCOVER_PHY */
 
-#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
+#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
 
 static int mii_init_done = 0;
 
@@ -585,17 +871,16 @@
  */
 void mii_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
-	bd_t *bd = gd->bd;
-
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
-	int i;
+	int i, j;
 
 	if (mii_init_done != 0) {
 		return;
 	}
 
+	for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
+
 	/* Whack a reset.
 	 * A delay is required between a reset of the FEC block and
 	 * initialization of other FEC registers because the reset takes
@@ -623,76 +908,19 @@
 	 */
 	fecp->fec_ievent = 0xffc0;
 
-	/* Set MII speed to 2.5 MHz or slightly below.
-	 * According to the MPC860T (Rev. D) Fast ethernet controller user
-	 * manual (6.2.14),
-	 * the MII management interface clock must be less than or equal
-	 * to 2.5 MHz.
-	 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
-	 * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
-	 */
-	fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
-
-#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
-	immr->im_ioport.iop_papar |=  0xf830;
-	immr->im_ioport.iop_padir |=  0x0830;
-	immr->im_ioport.iop_padir &= ~0xf000;
-	immr->im_cpm.cp_pbpar     |=  0x00001001;
-	immr->im_cpm.cp_pbdir     &= ~0x00001001;
-	immr->im_ioport.iop_pcpar |=  0x000c;
-	immr->im_ioport.iop_pcdir &= ~0x000c;
-	immr->im_ioport.iop_pdpar |=  0x0080;
-	immr->im_ioport.iop_pddir &= ~0x0080;
-	immr->im_cpm.cp_pepar     |=  0x00000003;
-	immr->im_cpm.cp_pedir     |=  0x00000003;
-	immr->im_cpm.cp_peso      &= ~0x00000003;
-#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
-	/* Configure all of port D for MII.
-	 */
-	immr->im_ioport.iop_pdpar = 0x1fff;
-
-	/* Bits moved from Rev. D onward */
-	if ((get_immr (0) & 0xffff) < 0x0501) {
-		immr->im_ioport.iop_pddir = 0x1c58;	/* Pre rev. D */
-	} else {
-		immr->im_ioport.iop_pddir = 0x1fff;	/* Rev. D and later */
-	}
-#else
-	/* Configure port A for MII.
+		/* Setup the pin configuration of the FEC(s)
 	*/
+		fec_pin_init(ether_fcc_info[i].ether_index);
 
-#if defined(CONFIG_ICU862)
-
-	/* On the ICU862 board the MII-MDC pin is routed to PD8 pin
-	 * of CPU, so for this board we need to configure Utopia and
-	 * enable PD8 to MII-MDC function */
-	immr->im_ioport.iop_pdpar |= 0x4080;
-#endif
-
-	/* Has Utopia been configured? */
-	if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
-		/*
-		 * YES - Use MUXED mode for UTOPIA bus.
-		 * This frees Port A for use by MII (see 862UM table 41-6).
-		 */
-		immr->im_ioport.utmode &= ~0x80;
-	} else {
-		/*
-		 * NO - set SPLIT mode for UTOPIA bus.
-		 *
-		 * This doesn't really effect UTOPIA (which isn't
-		 * enabled anyway) but just tells the 862
-		 * to use port A for MII (see 862UM table 41-6).
-		 */
-		immr->im_ioport.utmode |= 0x80;
-	}
-#endif	/* !defined(CONFIG_ICU862) */
 	/* Now enable the transmit and receive processing
 	 */
 	fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+	}
 
 	mii_init_done = 1;
+
 }
+
 /*****************************************************************************
  * Read and write a MII PHY register, routines used by MII Utilities
  *
diff -ruNb u-boot-original/include/asm-ppc/8xx_immap.h u-boot-fec/include/asm-ppc/8xx_immap.h
--- u-boot-original/include/asm-ppc/8xx_immap.h	2004-03-30 14:37:28.780913544 +0300
+++ u-boot-fec/include/asm-ppc/8xx_immap.h	2004-03-30 15:43:35.258917232 +0300
@@ -473,7 +473,11 @@
 	union	fec_lcd	fl_un;
 #define cp_fec		fl_un.fl_un_fec
 #define lcd_cmap	fl_un.fl_un_cmap
-	char	res18[0x1000];
+	char	res18[0xE00];
+
+	/* The DUET family has a second FEC here */
+	fec_t	cp_fec2;
+#define cp_fec1	cp_fec	/* consistency macro */
 
 	/* Dual Ported RAM follows.
 	 * There are many different formats for this memory area
diff -ruNb u-boot-original/include/mpc8xx.h u-boot-fec/include/mpc8xx.h
--- u-boot-original/include/mpc8xx.h	2004-03-30 14:37:28.755917344 +0300
+++ u-boot-fec/include/mpc8xx.h	2004-03-30 16:07:08.545065080 +0300
@@ -208,6 +208,12 @@
 #define SCCR_DFBRG10	0x00001000	/* BRGCLK division by 16		*/
 #define SCCR_DFBRG11	0x00001800	/* BRGCLK division by 64		*/
 #define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
+#define SCCR_DFNL001	0x00000100	/* Division by 4 	                */
+#define SCCR_DFNL010	0x00000200	/* Division by 8 	                */
+#define SCCR_DFNL011	0x00000300	/* Division by 16 	                */
+#define SCCR_DFNL100	0x00000400	/* Division by 32 	                */
+#define SCCR_DFNL101	0x00000500	/* Division by 64 	                */
+#define SCCR_DFNL110	0x00000600	/* Division by 128 	                */
 #define SCCR_DFNL111	0x00000700	/* Division by 256 (maximum)		*/
 #define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
 #define SCCR_DFNH110	0x000000D0	/* Division by 64 (maximum)		*/