[U-Boot] still nothing on serial output sa1100
Kristoffer Ericson
kristoffer.ericson at gmail.com
Tue Sep 15 22:31:47 CEST 2009
Greetings,
Ive been busy trying to get any signs from my generated
u-boot.bin.
I started thinking it was caused by the memory setup
and replicated the one I had used in blob (which works).
Still got nothing and now Im looking for suggestions on
where to proceed. Can I count on the serial drivers
working? What process starts after the memory is setup?
Attached my current Setup.S:
diff --git a/board/jornada/setup.S b/board/jornada/setup.S
new file mode 100644
index 0000000..1c6e233
--- /dev/null
+++ b/board/jornada/setup.S
@@ -0,0 +1,226 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw at its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker at its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG 0x00
+#define MDCAS00 0x04
+#define MDCAS01 0x08
+#define MDCAS02 0x0C
+#define MSC0 0x10
+#define MSC1 0x14
+#define MECR 0x18
+#define MDREFR 0x1C
+#define MDCAS20 0x20
+#define MDCAS21 0x24
+#define MDCAS22 0x28
+#define MSC2 0x2C
+#define SMCNFG 0x30
+
+#define MDCNFG_BANK0_ENABLE (1 << 0)
+#define MDCNFG_DTIM0_SDRAM (1 << 2)
+#define MDCNFG_DWID0_32B (0 << 3)
+#define MDCNFG_DRAC0(n_) (((n_) & 7) << 4)
+#define MDCNFG_TRP0(n_) (((n_) & 0xF) << 8)
+#define MDCNFG_TDL0(n_) (((n_) & 3) << 12)
+#define MDCNFG_TWR0(n_) (((n_) & 3) << 14)
+#define MSC_RT_ROMFLASH 0
+#define MSC_RBW32 (0 << 2)
+#define MSC_RDF(n_) (((n_) & 0x1f) << 3)
+#define MSC_RDN(n_) (((n_) & 0x1f) << 8)
+#define MSC_RRR(n_) (((n_) & 0x07) << 13)
+#define MSC_RT_VARLAT_345 1
+#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
+#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
+#define MDREFR_K0RUN (1 << 17)
+#define MDREFR_K0DB2 (1 << 18)
+#define MDREFR_K1RUN (1 << 21)
+#define MDREFR_K1DB2 (1 << 22)
+#define MDREFR_K2RUN (1 << 25)
+#define MDREFR_K2DB2 (1 << 26)
+#define MDREFR_SLFRSH (1 << 31)
+#define MDREFR_E1PIN (1 << 20)
+#define PSSR_DH 0x00000008
+#define PSSR 0x04
+#define PM_BASE 0x90020000
+
+#define mdcnfg_1 (MDCNFG_BANK0_ENABLE|MDCNFG_DTIM0_SDRAM|MDCNFG_DWID0_32B|MDCNFG_DRAC0(6)|MDCNFG_TRP0(2)|MDCNFG_TDL0(3)|MDCNFG_TWR0(1))
+#define cs0_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(15)|MSC_RDN(15)|MSC_RRR(2))
+#define cs1_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7))
+#define cs2_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7))
+#define cs3_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7))
+#define cs4_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(11)|MSC_RDN(9)|MSC_RRR(1))
+#define cs5_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(3)|MSC_RDN(0)|MSC_RRR(1))
+#define msc0_1 (cs0_1|(cs1_1 << 16))
+#define msc1_1 (cs2_1|(cs3_1 << 16))
+#define msc2_1 (cs4_1|(cs5_1 << 16))
+
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+
+
+MEM_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
+PWR_BASE: .word PM_BASE
+
+/* calculated from old blob bootloader */
+MEMORY_CONFIG:
+ .long mdcnfg_1 /* mdcnfg 0x00007265 */
+ .long 0x5555557f /* mdcas00 0x5555557f */
+ .long 0x55555555 /* mdcas01 0x55555555 */
+ .long 0x55555555 /* mdcas02 0x55555555 */
+ .long msc0_1 /* msc0 0xfff04f78 */
+ .long msc1_1 /* msc1 0xfff8fff0 */
+ .long 0x98c698c6 /* mecr 0x98c698c6 */
+ .long 0xdeadbeef /* mdrefr 0x04340327 */
+ .long 0xd1284142 /* mdcas20 0xd1284142 */
+ .long 0x72249529 /* mdcas21 0x72249529 */
+ .long 0x78414351 /* mdcas22 0x78414351 */
+ .long msc2_1 /* msc2 0x201d2959 */
+ .long 0x00000000 /* smcnfg 0x00000000 */
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r5, lr
+
+ /* Setting up the memory and stuff */
+ ldr r0, MEM_BASE
+ adr r1, MEMORY_CONFIG
+
+ ldr r2, [r1, #MDCNFG]
+ str r2, [r0, #MDCNFG]
+
+ ldr r2, [r1, #MDCAS00]
+ str r2, [r0, #MDCAS00]
+
+ ldr r2, [r1, #MDCAS01]
+ str r2, [r0, #MDCAS01]
+
+ ldr r2, [r1, #MDCAS02]
+ str r2, [r0, #MDCAS02]
+
+ ldr r2, [r1, #MDCAS20]
+ str r2, [r0, #MDCAS20]
+
+ ldr r2, [r1, #MDCAS21]
+ str r2, [r0, #MDCAS21]
+
+ ldr r2, [r1, #MDCAS22]
+ str r2, [r0, #MDCAS22]
+
+ /* clear kxDB2 */
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ /* set TRASR and DRI, KXDB2 */
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+
+ mov r4, #0x2000
+spin: subs r4, r4, #1
+ bne spin
+
+ ldr r1, PWR_BASE
+ mov r2, #PSSR_DH
+ str r2, [r1, #PSSR]
+
+ /* clear KxDB2 */
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ /* set TRASR and DRI, KxDB2 */
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+ orr r2, r2, #MDREFR_DRI(12)
+ orr r2, r2, #MDREFR_K0DB2
+ orr r2, r2, #MDREFR_K1DB2
+ orr r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ /* set KxRUN */
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_K0RUN
+ orr r2, r2, #MDREFR_K1RUN
+ orr r2, r2, #MDREFR_K2RUN
+ str r2, [r0, #MDREFR]
+
+ /* clear SLFRSH */
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_SLFRSH
+ str r2, [r0, #MDREFR]
+
+ /* toggle E1PIN (set -> clear) */
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_E1PIN
+ str r2, [r0, #MDREFR]
+
+ /* Load something to activate bank */
+ ldr r1, MEM_START
+.rept 8
+ ldr r0, [r1]
+.endr
+
+ ldr r0, MEM_BASE
+ adr r1, MEMORY_CONFIG
+
+ /* Enable SDRAM banks */
+ ldr r2, [r0, #MDCNFG]
+ orr r2, r2, #0x00000003
+ orr r2, r2, #0x00030000
+ str r2, [r0, #MDCNFG]
+
+ ldr r2, [r1, #MSC0]
+ str r2, [r0, #MSC0]
+
+ ldr r2, [r1, #MSC1]
+ str r2, [r0, #MSC1]
+
+ ldr r2, [r1, #MSC2]
+ str r2, [r0, #MSC2]
+
+ ldr r2, [r1, #SMCNFG]
+ str r2, [r0, #SMCNFG]
+
+ ldr r2, [r1, #MECR]
+ str r2, [r0, #MECR]
+
+ /* All done... */
+ mov pc, r5
--
Kristoffer Ericson <kristoffer.ericson at gmail.com>
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