[U-Boot] [PATCH v4 3/4] EHCI: adjust for mx5

[Jana Rapava]

2011/11/14 Wolfgang Grandegger <wg at denx.de>

>
> >
> > +#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
> > +#define USBCTRL_OTGBASE_OFFSET       0x600
> > +#endif
> > +
> > +#ifdef CONFIG_MX25
> > +#define MX25_USB_CTRL_IP_PUE_DOWN_BIT        (1<<6)
> > +#define MX25_USB_CTRL_HSTD_BIT               (1<<5)
> > +#define MX25_USB_CTRL_USBTE_BIT      (1<<4)
> > +#define MX25_USB_CTRL_OCPOL_OTG_BIT  (1<<3)
> > +#endif
> > +
> > +#ifdef CONFIG_MX31
> > +#define MX31_H2_SIC_SHIFT    21
> > +#define MX31_H2_SIC_MASK     (0x3 << MX31_H2_SIC_SHIFT)
> > +#define MX31_H2_PM_BIT               (1 << 16)
> > +#define MX31_H2_DT_BIT               (1 << 5)
> > +
> > +#define MX31_H1_SIC_SHIFT    13
> > +#define MX31_H1_SIC_MASK     (0x3 << MX31_H1_SIC_SHIFT)
> > +#define MX31_H1_PM_BIT               (1 << 8)
> > +#define MX31_H1_DT_BIT               (1 << 4)
> > +#endif
> > +
> > +#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
> > +/* offset for first USB CTRL register */
> > +#define MX5_CTRL_REGS_OFFSET 0x800
> > +#endif
> > +
> > +#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
> > +/* USB_CTRL register bits of interest*/
> > +#define MXC_OTG_SIC_SHIFT    29
> > +#define MXC_OTG_SIC_MASK     (0x3 << MX31_OTG_SIC_SHIFT)
> > +#define MXC_OTG_WUE          (1 << 27)
> > +#define MXC_OTG_PM           (1 << 24)
> > +#endif
> > +
> > +#ifdef CONFIG_MX51
> > +#define MX51_REGISTER_LAYOUT_LENGTH  0x200
> > +
> > +/* Register offsets for MX51 */
> > +#define MX51_OTG_ID  0x000
> > +#define MX51_UH1_ID  0x200
> > +#define MX51_UH2_ID  0x400
> > +
> > +/* USB_CTRL register bits of interest*/
> > +#define MX51_OTG_PM          (1 << 24)
> > +#define MX51_H1_ULPI_IE      (1 << 12)
> > +#define MX51_H1_WUE          (1 << 11)
> > +#define MX51_H1_PM           (1 << 8)
> > +
> > +/* PHY_CTRL_0 register bits of interest */
> > +#define MX51_OTG_OVERCURD    (1 << 8)
> > +#define MX51_EHCI_POWERPINSE (1 << 5)
> > +
> > +/* PHY_CTRL_1 register bits of interest */
> > +#define MX51_SYSCLOCK_24_MHZ (1 << 0)
> > +#define MX51_SYSCLOCK_MASK   (~(0xffffffff << 2))
> > +
> > +/* USB_CTRL_1 register bits of interest */
> > +#define MX51_H1_EXTCLKE      (1 << 25)
> > +
> > +/* USB Host 2 CTRL register bits of interest */
> > +#define MX51_H2_ULPI_IE      (1 << 8)
> > +#define MX51_H2_WUE          (1 << 7)
> > +#define MX51_H2_PM           (1 << 4)
>
> Most of the definitions above are arch specific and would better be
> placed in arch/arm/include/asm/arch-mx25/31/5, I think.
>
> Stefano, what do you think? You said that these definitions could be in
ehci-fsl.h, is arch-specific place better?


> > +/* PORTSCx bits of interest */
> > +#define MX51_ULPI_MODE_MASK  (2 << 30)
> > +#define MX51_16BIT_UTMI      (1 << 28)
>
> In ehci-fsl.h we have already
>
>  #define PORT_PTS_ULPI           (2 << 30)
>  #define PORT_PTS_PTW            (1 << 28)
>
> Ok, I'll use them.
Regards,
Jana Rapava