[U-Boot] [PATCH u-boot-arm/next v2 1/1] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Enric Balletbò i Serra]

2012/7/19 Javier Martinez Canillas <javier at dowhile0.org>:
> On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra
> <eballetbo at gmail.com> wrote:
>> 2012/7/19 Javier Martinez Canillas <javier at dowhile0.org>:
>>> On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni
>>> <thomas.petazzoni at free-electrons.com> wrote:
>>>> Le Tue, 17 Jul 2012 02:15:17 +0200,
>>>> Javier Martinez Canillas <javier at dowhile0.org> a écrit :
>>>>
>>>>> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
>>>>> +             u32 *mr)
>>>>> +{
>>>>> +     *mr = MICRON_V_MR_165;
>>>>> +#ifdef CONFIG_BOOT_NAND
>>>>> +     *mcfg = MICRON_V_MCFG_165(512 << 20);
>>>>> +     *ctrla = MICRON_V_ACTIMA_165;
>>>>> +     *ctrlb = MICRON_V_ACTIMB_165;
>>>>> +     *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>>>>
>>>> I thought the NAND version of the IGEPv2 was capable of using the 200
>>>> Mhz timings. At least, from the limited testing I had done, it seemed
>>>> to work.
>>>>
>>>> Best regards,
>>>>
>>>> Thomas
>>>> --
>>>
>>> Hi Thomas,
>>>
>>> Yes, you are right. I just tested the following patch on my NAND
>>> version IGEPv2 and it seems to work just fine.
>>>
>>> Do you know if the OneNAND version also supports 200 MHz timings? If I
>>> remember correctly the OMAP3730 version did but the OMAP3530 didn't.
>>>
>>> I guess Enric knows the answer :-)
>>>
>>
>> Both memories can work at 200MHz, I guess the limitation is on the
>> processor that is populated on the board. If the IGEP board comes with
>> OMAP3530 should work at 166MHz, if comes with DM3730 can work at
>> 200MHz.
>>
>> Cheers,
>>    Enric
>
> Hi Enric,
>
> That's what I remembered but I wasn't sure about it, thanks for the
> clarification.
>
> What do you think about this patch then?
>
> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
> index 40436d6..a4d099a 100644
> --- a/board/isee/igep0020/igep0020.c
> +++ b/board/isee/igep0020/igep0020.c
> @@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
> u32 *ctrlb, u32 *rfr_ctrl,
>  {
>         *mr = MICRON_V_MR_165;
>  #ifdef CONFIG_BOOT_NAND
> -       *mcfg = MICRON_V_MCFG_165(512 << 20);
> -       *ctrla = MICRON_V_ACTIMA_165;
> -       *ctrlb = MICRON_V_ACTIMB_165;
> -       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +       *mcfg = MICRON_V_MCFG_200(512 << 20);
> +       *ctrla = MICRON_V_ACTIMA_200;
> +       *ctrlb = MICRON_V_ACTIMB_200;
> +       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>  #else
> -       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> -       *ctrla = NUMONYX_V_ACTIMA_165;
> -       *ctrlb = NUMONYX_V_ACTIMB_165;
> -       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +       if (get_cpu_family() == CPU_OMAP34XX) {
> +               *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> +               *ctrla = NUMONYX_V_ACTIMA_165;
> +               *ctrlb = NUMONYX_V_ACTIMB_165;
> +               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +
> +       } else {
> +               *mcfg = NUMONYX_V_MCFG_200(512 << 20);
> +               *ctrla = NUMONYX_V_ACTIMA_200;
> +               *ctrlb = NUMONYX_V_ACTIMB_200;
> +               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> +       }
>  #endif
>  }
>  #endif
> diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
> index 41a7548..4f8b645 100644
> --- a/board/isee/igep0030/igep0030.c
> +++ b/board/isee/igep0030/igep0030.c
> @@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
> u32 *ctrlb, u32 *rfr_ctrl,
>  {
>         *mr = MICRON_V_MR_165;
>  #ifdef CONFIG_BOOT_NAND
> -       *mcfg = MICRON_V_MCFG_165(512 << 20);
> -       *ctrla = MICRON_V_ACTIMA_165;
> -       *ctrlb = MICRON_V_ACTIMB_165;
> -       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +       *mcfg = MICRON_V_MCFG_200(512 << 20);
> +       *ctrla = MICRON_V_ACTIMA_200;
> +       *ctrlb = MICRON_V_ACTIMB_200;
> +       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>  #else
> -       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> -       *ctrla = NUMONYX_V_ACTIMA_165;
> -       *ctrlb = NUMONYX_V_ACTIMB_165;
> -       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +       if (get_cpu_family() == CPU_OMAP34XX) {
> +               *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> +               *ctrla = NUMONYX_V_ACTIMA_165;
> +               *ctrlb = NUMONYX_V_ACTIMB_165;
> +               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +
> +       } else {
> +               *mcfg = NUMONYX_V_MCFG_200(512 << 20);
> +               *ctrla = NUMONYX_V_ACTIMA_200;
> +               *ctrlb = NUMONYX_V_ACTIMB_200;
> +               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> +       }
>  #endif
>  }
>  #endif

Thanks Thomas for making this observation.

Javier, the patch looks good for me. If we have the Numonyx OneNAND we
should check if the processor is OMAP3530 or DM3730 and apply the
correct timings. If we have the Micron NAND memory this check is not
necessary because all boards with this memory uses DM3730.

Cheers,
   Enric