[U-Boot] [PATCH] fsl_esdhc: Touch only relevant sys ctrl bits

[Stefano Babic]

On 15/07/2013 15:44, Dirk Behme wrote:
> Dealing with the sys ctrl register should touch only the
> relevant bits and not accidently the whole register. On i.MX6,
> the sys control register contains bits which shouldn't be reset to
> 0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]).
> 
> Do this by read/modify/write instead of just a 32bit write.
> 
> Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>
> ---
>  drivers/mmc/fsl_esdhc.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 973b19f..431dac2 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -470,7 +470,7 @@ static int esdhc_init(struct mmc *mmc)
>  	int timeout = 1000;
>  
>  	/* Reset the entire host controller */
> -	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
> +	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
>  
>  	/* Wait until the controller is available */
>  	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
> @@ -481,7 +481,7 @@ static int esdhc_init(struct mmc *mmc)
>  	esdhc_write32(&regs->scr, 0x00000040);
>  #endif
>  
> -	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
> +	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
>  
>  	/* Set the initial clock speed */
>  	mmc_set_clock(mmc, 400000);
> @@ -515,7 +515,7 @@ static void esdhc_reset(struct fsl_esdhc *regs)
>  	unsigned long timeout = 100; /* wait max 100 ms */
>  
>  	/* reset the controller */
> -	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
> +	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
>  
>  	/* hardware clears the bit when it is done */
>  	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
> 

Acked-by: Stefano Babic <sbabic at denx.de>

Best regards,
Stefano Babic

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