[U-Boot] [PATCH] board/ls2080rdb, qds: Enable ddr hashing for controller version 5.2.1

[york sun]

On 11/17/2016 10:43 PM, Priyanka Jain wrote:
>
>
>> -----Original Message-----
>> From: york sun
>> Sent: Thursday, November 17, 2016 10:14 PM
>> To: Priyanka Jain <priyanka.jain at nxp.com>; u-boot at lists.denx.de
>> Subject: Re: [PATCH] board/ls2080rdb,qds: Enable ddr hashing for controller
>> version 5.2.1
>>
>> On 11/17/2016 01:39 AM, Priyanka Jain wrote:
>>> From: Priyanka Jain <priyanka.jain at nxp.com>
>>>
>>> Enable DDR hashing for DDR performance optimization on LS2088A which
>>> has DDR controller version 5.2.1
>>>
>>> Signed-off-by: Priyanka Jain <priyanka.jain at nxp.com>
>>> ---
>>>  board/freescale/ls2080aqds/ddr.c |    5 +++++
>>>  board/freescale/ls2080ardb/ddr.c |    5 +++++
>>>  2 files changed, 10 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/board/freescale/ls2080aqds/ddr.c
>>> b/board/freescale/ls2080aqds/ddr.c
>>> index 9c6f477..473dd7c 100644
>>> --- a/board/freescale/ls2080aqds/ddr.c
>>> +++ b/board/freescale/ls2080aqds/ddr.c
>>> @@ -8,6 +8,7 @@
>>>  #include <fsl_ddr_sdram.h>
>>>  #include <fsl_ddr_dimm_params.h>
>>>  #include <asm/arch/soc.h>
>>> +#include <fsl_ddr.h>
>>>  #include "ddr.h"
>>>
>>>  DECLARE_GLOBAL_DATA_PTR;
>>> @@ -134,6 +135,10 @@ found:
>>>  	/* Enable ZQ calibration */
>>>  	popts->zq_en = 1;
>>>
>>> +	/* Enable DDR hashing */
>>> +	if (fsl_ddr_get_version(0) == 0x50201)
>>> +		popts->addr_hash = 1;
>>> +
>>
>> We already have this option. You simply need to set it in hwconfig.
>>
>> York
> SoC performance team has recommended to keep DDR hashing enabled by default for LS2088A for better performance.
> Shall we make this change or change hwconfig setting in env?

I don't support enabling it by default. Please note, this feature is not 
even disclosed in any public reference manual.

York