[U-Boot-Users] mtmsr causes an exception (it was "Problem wi

llandre r&d at wawnet.biz
Wed Apr 2 10:45:44 CEST 2003

 >What is the value you are moving into the MSR? What processor are you
 >using? Is this a board with existing support or a custom board? Does it
 >work if you don't step through that instruction using the BDI2000?

Hi Gerald.
I'm using the IBM evaluation board for the PPC 405EP.
I debug the code in the SRAM connected to the PerCS0 chip select (it can be 
exchanged with the boot Flash). The first instructions are:
        b _start
        addi     r4,r0,0x0000
         mtspr   sgr,r4
         mtspr   dcwr,r4
         mtesr   r4                      /* clear Exception Syndrome Reg */
         mttcr   r4                      /* clear Timer Control Reg */
         mtxer   r4                      /* clear Fixed-Point Exception Reg */
         mtevpr  r4                      /* clear Exception Vector Prefix 
Reg */
         addi    r4,r0,0x1000            /* set ME bit (Machine Exceptions) */
         oris    r4,r4,0x0002            /* set CE bit (Critical Exceptions) */
         mtmsr   r4                      /* change MSR */
         addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF 
(status in the */

When I execute step-by-step this code, the instruction mtmsr makes the CPU 
to jump to 0x700.
I suspect it is due to the uncorrect script I use for the Abatron BDI2000. 
For convenience I copied it at the bottom of the message. I derived it from 
the example shipped with the BDI that is written for the 405GP board 
(Walnut). In order to simulate the state of the hardware just after a 
reset, I removed a lot of initializations.
If I burn the code into Flash, that instruction works (but it crashes 
somewhere after).

;bdiGDB configuration file for IBM 405EP Reference Board for U-Boot
; -----------------------------------------------------------------
; init core register
;WSPR   954     0x00000000      ;DCWR: Disable data cache write-thru
;WSPR   1018    0x00000000      ;DCCR: Disable data cache
;WSPR   1019    0x00000000      ;ICCR: Disable instruction cache
;WSPR   982     0x00000000      ;EVPR: Exception Vector Table @0x00000000

; Setup Peripheral Bus
WDCR    18      0x00000010      ;Select PB0AP
WDCR    19      0x9B015480      ;PB0AP: Flash and SRAM
WDCR    18      0x00000000      ;Select PB0CR
WDCR    19      0xFFF18000      ;PB0CR: 1MB at 0xFFF00000, r/w, 8bit

;WDCR   18      0x00000011      ;Select PB1AP
;WDCR   19      0x02815480      ;PB1AP: NVRAM and RTC
;WDCR   18      0x00000001      ;Select PB1CR
;WDCR   19      0xF0018000      ;PB1CR: 1MB at 0xF0000000, r/w, 8bit
;WDCR   18      0x00000012      ;Select PB2AP
;WDCR   19      0x04815A80      ;PB2AP: Keyboard and Mouse
;WDCR   18      0x00000002      ;Select PB2CR
;WDCR   19      0xF0118000      ;PB2CR: 1MB at 0xF0100000, r/w, 8bit
;WDCR   18      0x00000013      ;Select PB3AP
;WDCR   19      0x01815280      ;PB3AP: IRDA
;WDCR   18      0x00000003      ;Select PB3CR
;WDCR   19      0xF0218000      ;PB3CR: 1MB at 0xF0200000, r/w, 8bit
;WDCR   18      0x00000017      ;Select PB7AP
;WDCR   19      0x01815280      ;PB7AP: FPGA
;WDCR   18      0x00000007      ;Select PB7CR
;WDCR   19      0xF0318000      ;PB7CR: 1MB at 0xF0300000, r/w, 8bit

; Setup SDRAM Controller
;WDCR   16      0x00000080      ;Select SDTR1
;WDCR   17      0x0086400D      ;SDTR1: SDRAM Timing Register
;WDCR   16      0x00000040      ;Select MB0CF
;WDCR   17      0x00046001      ;MB0CF: 16MB @ 0x00000000
;WDCR   16      0x00000048      ;Select MB2CF
;WDCR   17      0x01046001      ;MB2CF: 16MB @ 0x01000000
;WDCR   16      0x00000030      ;Select RTR
;WDCR   17      0x05F00000      ;RTR: Refresh Timing Register
;WDCR   16      0x00000020      ;Select MCOPT1
;WDCR   17      0x80800000      ;MCOPT1: Enable SDRAM Controller

; Setup MMU info
;WM32    0x000000f4  0x00000000  ;invalidate kernel  page table base
;WM32    0x000000f8  0x00000000  ;invalidate process page table base
;WM32    0x000000f0  0xc00000f4  ;invalidate page table base

JTAGCLOCK   0                   ;use 16 MHz JTAG clock
CPUTYPE     405                 ;the used target CPU type
BDIMODE     AGENT               ;the BDI working mode (LOADONLY | AGENT)
;WAKEUP      3000                ;wakeup time after reset
BREAKMODE   HARD                ;SOFT or HARD, HARD uses PPC hardware 
STEPMODE    HWBP                ;JTAG or HWBP, HWPB uses one or two 
hardware breakpoints
;VECTOR      CATCH               ;catch unhandled exceptions
;MMU         XLAT 0xC0000000     ;enable virtual address mode
;PTBASE      0x000000f0          ;address where kernel/user stores pointer 
to page table
;SIO         7 9600              ;TCP port for serial IO

;REGLIST     SPR                 ;select register to transfer to GDB
REGLIST     ALL                 ;select register to transfer to GDB
;SCANPRED    2 2                 ;JTAG devices connected before PPC400
;SCANSUCC    3 3                 ;JTAG devices connected after PPC400

IP       ;Linux host
;IP      ;Windows host
;FILE        E:\cygwin\home\bdidemo\evb405\vxworks
FILE        /tftpboot/u-boot
FILE        u-boot
LOAD        MANUAL        ;load code MANUAL or AUTO after reset
;LOAD        AUTO
;DUMP        E:\temp\dump.bin
DUMP        dump.bin            ;Linux: dump.bin must already exist and 
public writable

WORKSPACE   0x00004000  ;workspace in target RAM for fast programming algorithm
CHIPTYPE    AM29F       ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | 
CHIPSIZE    0x80000     ;The size of one flash chip in bytes (e.g. AM29F040 
= 0x80000)
BUSWIDTH    8           ;The width of the flash memory bus in bits (8 | 16 
| 32)
FILE        E:\cygwin\home\bdidemo\evb405\evb405gp.sss  ;The file to program
ERASE       0xFFF80000  ;erase sector 0 of flash in U7 (AM29F040)
ERASE       0xFFF90000  ;erase sector 1 of flash
ERASE       0xFFFA0000  ;erase sector 2 of flash
ERASE       0xFFFB0000  ;erase sector 3 of flash
ERASE       0xFFFC0000  ;erase sector 4 of flash
ERASE       0xFFFD0000  ;erase sector 5 of flash
ERASE       0xFFFE0000  ;erase sector 6 of flash
ERASE       0xFFFF0000  ;erase sector 7 of flash

IDCR1   0x010   0x011   ;MEMCFGADR and MEMCFGDATA
IDCR2   0x012   0x013   ;EBCCFGADR and EBCCFGDATA
;IDCR3  0x014   0x015   ;KIAR and KIDR
;FILE    E:\cygwin\home\bdidemo\evb405\reg405gp.def
FILE    reg405ep.def


More information about the U-Boot mailing list