[U-Boot-Users] RE: More On Memory Bank x (nothingness)?
Jerry Walden
jwalden at digitalatlantic.com
Mon Feb 10 21:54:07 CET 2003
To add more detail to my previous question - The Walnut config has
CFG_INIT_DCACHE_INIT_CS = 4, however if we look at the schematic for the
Walnut board we do not see anything hooked up to the peripheral bus on
chip select 4, so what am I missing?
Can someone explain what the difference is between DCACHE and OCM for the
405GP?
Since our board certainly does not have any memory on CS=4, then do I have
to go through and set up the stack in OCM?
If I have to set up the stack in OCM, is see in start.S that the following
section
of code are executed:
What should CFG_OCM_DATA_ADDR be, and to what does it refer?
What should CFG_INIT_RAM_ADDR be based on the above answer?
#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
/********************************************************************
* Setup OCM - On Chip Memory
*******************************************************************/
/* Setup OCM */
lis r0, 0x7FFF
ori r0, r0, 0xFFFF
mfdcr r3, ocmiscntl /* get instr-side IRAM config */
mfdcr r4, ocmdscntl /* get data-side IRAM config */
and r3, r3, r0 /* disable data-side IRAM */
and r4, r4, r0 /* disable data-side IRAM */
mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
mtdcr ocmdscntl, r4 /* set data-side IRAM config */
isync
addis r3, 0, CFG_OCM_DATA_ADDR at h /* OCM location */
mtdcr ocmdsarc, r3
addis r4, 0, 0xC000 /* OCM data area enabled */
mtdcr ocmdscntl, r4
isync
#endif
/*
* Stack in OCM.
*/
/* Set up Stack at top of OCM */
lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
/* Set up a zeroized stack frame so that backtrace works right */
li r0, 0
stwu r0, -4(r1)
stwu r0, -4(r1)
/*
* Set up a dummy frame to store reset vector as return address.
* this causes stack underflow to reset board.
*/
stwu r1, -8(r1) /* Save back chain and move SP */
lis r0, RESET_VECTOR at h /* Address of reset vector */
ori r0, r0, RESET_VECTOR at l
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save return addr (underflow vect) */
Jerry
-----Original Message-----
From: Jerry Walden [mailto:jwalden at digitalatlantic.com]
Sent: Monday, February 10, 2003 2:26 PM
To: u-boot-users at lists.sourceforge.net
Subject: Memory Bank x (nothingness)?
Greetings -
I have a custom PPC405GPr board, and I am trying to bring u-boot up on it.
/*-----------------------------------------------------------------------
*/
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/* Memory Bank x (nothingness) initialization 1GB+64MEG */
/* used as temporary stack pointer for stage0 */
/*-----------------------------------------------------------------------
*/
li r4,PBxAP
mtdcr ebccfga,r4
lis r4,0x0380
ori r4,r4,0x0480
mtdcr ebccfgd,r4
The Walnut config has CFG_INIT_DCACHE_INIT_CS = 4
In our custom board do not have anything attached to bank 4 -
Does DCACHE for the processors cache or programmers private use?
How can I (or how should I) re-write/add/subtract the above code to
accomplish
what it is trying to do (which is not clear to me).
Thanks
Jerry Walden
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