[U-Boot-Users] Patch: New PowerQUICC II processors support
Yuli Barcohen
yuli at arabellasw.com
Sun Jul 13 20:11:06 CEST 2003
Latest additions to PowerQUICC II family (8270/8275/8280) have got
different PVR values and different clock generation scheme. This patch
adds support for these processors.
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli at arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================
-------------- next part --------------
diff -purN CVS/cpu/mpc8260/commproc.c Arabella/cpu/mpc8260/commproc.c
--- CVS/cpu/mpc8260/commproc.c 2003-07-13 20:49:08.000000000 +0300
+++ Arabella/cpu/mpc8260/commproc.c 2003-07-13 20:59:49.000000000 +0300
@@ -111,9 +111,9 @@ m8260_cpm_hostalloc(uint size, uint alig
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK gd->brg_clk
-#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
+#define BRG_UART_CLK (BRG_INT_CLK / 16)
-/* This function is used by UARTS, or anything else that uses a 16x
+/* This function is used by UARTs, or anything else that uses a 16x
* oversampled clock.
*/
void
@@ -123,9 +123,10 @@ m8260_cpm_setbrg(uint brg, uint rate)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uint *bp;
+ uint cd = BRG_UART_CLK / rate;
- /* This is good enough to get SMCs running.....
- */
+ if ((BRG_UART_CLK % rate) < (rate / 2))
+ cd--;
if (brg < 4) {
bp = (uint *)&immr->im_brgc1;
}
@@ -134,7 +135,7 @@ m8260_cpm_setbrg(uint brg, uint rate)
brg -= 4;
}
bp += brg;
- *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
+ *bp = (cd << 1) | CPM_BRG_EN;
}
/* This function is used to set high speed synchronous baud rate
diff -purN CVS/cpu/mpc8260/cpu.c Arabella/cpu/mpc8260/cpu.c
--- CVS/cpu/mpc8260/cpu.c 2003-07-13 20:26:46.000000000 +0300
+++ Arabella/cpu/mpc8260/cpu.c 2003-07-13 20:37:50.000000000 +0300
@@ -22,7 +22,7 @@
*/
/*
- * CPU specific code for the MPC8255 / MPC8260 CPUs
+ * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
*
* written or collected and sometimes rewritten by
* Magnus Damm <damm at bitsmart.com>
@@ -35,6 +35,9 @@
*
* added 8260 masks by
* Marius Groeger <mag at sysgo.de>
+ *
+ * added HiP7 (8270/8275/8280) processors support by
+ * Yuli Barcohen <yuli at arabellasw.com>
*/
#include <common.h>
@@ -56,15 +59,27 @@ int checkcpu (void)
puts ("CPU: ");
- if (((pvr >> 16) & 0xff) != 0x81)
+ switch (pvr) {
+ case PVR_8260:
+ case PVR_8260_HIP3:
+ strcpy (buf, "HiP3");
+ break;
+ case PVR_8260_HIP4:
+ strcpy (buf, "HiP4");
+ break;
+ case PVR_8260_HIP7:
+ strcpy (buf, "HiP7");
+ break;
+ default:
return -1; /* whoops! not an MPC8260 */
+ }
rev = pvr & 0xff;
immr = immap->im_memctl.memc_immr;
if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
return -1; /* whoops! someone moved the IMMR */
- printf (CPU_ID_STR " (Rev %02x, Mask ", rev);
+ printf (CPU_ID_STR " (%s Rev %02x, Mask ", buf, rev);
/*
* the bottom 16 bits of the immr are the Part Number and Mask Number
@@ -104,6 +119,12 @@ int checkcpu (void)
case 0x0062:
printf ("B.1 4K25A");
break;
+ case 0x0A00:
+ printf ("0.0 0K49M");
+ break;
+ case 0x0A01:
+ printf ("0.1 1K49M");
+ break;
default:
printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
break;
diff -purN CVS/cpu/mpc8260/speed.c Arabella/cpu/mpc8260/speed.c
--- CVS/cpu/mpc8260/speed.c 2003-07-13 20:51:15.000000000 +0300
+++ Arabella/cpu/mpc8260/speed.c 2003-07-13 17:27:30.000000000 +0300
@@ -120,15 +120,19 @@ int get_clocks (void)
scmr = immap->im_clkrst.car_scmr;
corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
- busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
- cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
- plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
- pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
-
cp = &corecnf_tab[corecnf];
- gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
+ busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
+ cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
+ if (get_pvr () == PVR_8260_HIP7) { /* HiP7 */
+ pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
+ gd->vco_out = clkin * (pllmf + 1);
+ } else { /* HiP3, HiP4 */
+ pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
+ plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
+ gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
+ }
#if 0
if (gd->vco_out / (busdf + 1) != clkin) {
/* aaarrrggghhh!!! */
diff -purN CVS/include/asm-ppc/processor.h Arabella/include/asm-ppc/processor.h
--- CVS/include/asm-ppc/processor.h 2003-07-13 20:27:48.000000000 +0300
+++ Arabella/include/asm-ppc/processor.h 2003-07-13 20:32:30.000000000 +0300
@@ -524,8 +524,15 @@
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
-#define PVR_8260 PVR_8240
+/*
+ * PowerQUICC II family processors report different PVR values depending
+ * on silicon process (HiP3, HiP4, HiP7, etc.)
+ */
+#define PVR_8260 PVR_8240
+#define PVR_8260_HIP3 0x00810101
+#define PVR_8260_HIP4 0x80811014
+#define PVR_8260_HIP7 0x80822011
/* I am just adding a single entry for 8260 boards. I think we may be
* able to combine mbx, fads, rpxlite, bseip, and classic into a single
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