[U-Boot-Users] Re: Problems with the port to PPC 405EP ev. board
llandre
r&d at wawnet.biz
Tue Mar 18 09:05:59 CET 2003
Since the source file exceeds the maximum allowed message size, I post the
diff (diff -u):
--- start.S 2003-02-12 09:33:46.000000000 +0100
+++ start.S.new 2003-03-17 17:11:32.000000000 +0100
@@ -504,7 +504,7 @@
#endif /* CONFIG_IOP480 */
/*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405)
|| defined(CONFIG_405EP)
/*-----------------------------------------------------------------------
*/
/* Clear and set up some registers. */
/*-----------------------------------------------------------------------
*/
@@ -517,7 +517,9 @@
mtevpr r4 /* clear Exception Vector Prefix
Reg */
addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
+#ifndef __DEBUG_START_FROM_SRAM__
mtmsr r4 /* change MSR */
+#endif
addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF
(status in the */
/* dbsr is cleared by setting bits
to 1) */
mtdbsr r4 /* clear/reset the dbsr */
@@ -544,7 +546,7 @@
addi r4,r4,0x0000
mtdccr r4 /* data cache */
-#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if (!(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) &&
!(defined(__DEBUG_START_FROM_SRAM__)))
/*-----------------------------------------------------------------------
*/
/* Tune the speed and size for flash CS0 */
/*-----------------------------------------------------------------------
*/
@@ -573,6 +575,51 @@
isync
#endif
+#if (defined(CONFIG_BUBINGA405EP) && defined(CONFIG_NO_SERIAL_EEPROM))
+ /*
+ !-----------------------------------------------------------------------
+ ! Check to see if chip is in bypass mode.
+ ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
+ ! CPU reset Otherwise, skip this step and keep going.
+ ! Note: Running BIOS in bypass mode is not supported since PLB speed
+ ! will not be fast enough for the SDRAM (min 66MHz)
+
!-----------------------------------------------------------------------
+ */
+ mfdcr r5, CPC0_PLLMR1
+ rlwinm r4,r5,1,0x1 /*! get system clock source (SSCS)*/
+ cmpi cr0,0,r4,0x1
+
+ beq pll_done /*! if SSCS =b'1' then PLL has */
+ /*! already been set */
+ /*! and CPU has been reset */
+ /*! so skip to next section */
+
+ /*
+
!-----------------------------------------------------------------------
+ ! Read NVRAM to get value to write in PLLMR.
+ ! If value has not been correctly saved, write default value
+ ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
+ ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
+ !
+ ! WARNING: This code assumes the first three words in the nvram_t
+ ! structure in openbios.h. Changing the beginning of
+ ! the structure will break this code.
+ !
+
!-----------------------------------------------------------------------
+ */
+ addis r3,0,PLLMR0_DEFAULT at h /*! PLLMR0 default value */
+ ori r3,r3,PLLMR0_DEFAULT at l
+ addis r4,0,PLLMR1_DEFAULT at h /*! PLLMR1 default value */
+ ori r4,r4,PLLMR1_DEFAULT at l
+
+
+ b pll_write /*! Write the CPC0_PLLMR with
new value*/
+
+
+
+pll_done:
+#endif /* (defined(CONFIG_BUBINGA405EP) &&
defined(CONFIG_NO_SERIAL_EEPROM)) */
+
/*-----------------------------------------------------------------------
*/
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*-----------------------------------------------------------------------
*/
@@ -692,6 +739,102 @@
#endif /* CONFIG_405GP || CONFIG_405CR */
+/*#if 0*/
+#if (defined(CONFIG_BUBINGA405EP) && defined(CONFIG_NO_SERIAL_EEPROM))
+/*
+!-----------------------------------------------------------------------------
+! Function: pll_write
+! Description: Updates the value of the CPC0_PLLMR according to CMOS27E
documentation
+! That is:
+! 1. Pll is first disabled (de-activated by
putting in bypass mode)
+! 2. PLL is reset
+! 3. Clock dividers are set while PLL is held in
reset and bypassed
+! 4. PLL Reset is cleared
+! 5. Wait 100us for PLL to lock
+! 6. A core reset is performed
+! Input: r3 = Value to write to CPC0_PLLMR0
+! Input: r4 = Value to write to CPC0_PLLMR1
+! Output r3 = none
+!-----------------------------------------------------------------------------
+*/
+/*
+ .text
+ .align 2
+*/
+ .globl pll_write
+pll_write:
+
+ lis r5,0x0500 /*! Wait approx. 1/4 second to
allow */
+ mtctr r5 /*! any transmitted characters on */
+ /*! UARTs to complete. Assume
333MHz. */
+uart_delay:
+ bdnz uart_delay
+
+ mfdcr r5, CPC0_UCR
+ andis. r5,r5,0xFFFF
+ ori r5,r5,0x0101 /*! Stop the UART clocks */
+ mtdcr CPC0_UCR,r5 /*! Before changing PLL */
+
+ mfdcr r5, CPC0_PLLMR1
+ rlwinm r5,r5,0,0x7FFFFFFF /*! Disable PLL */
+ mtdcr CPC0_PLLMR1,r5
+ oris r5,r5,0x4000 /*! Set PLL Reset */
+ mtdcr CPC0_PLLMR1,r5
+
+ mtdcr CPC0_PLLMR0,r3 /*! Set clock dividers */
+ rlwinm r5,r4,0,0x3FFFFFFF /*! Reset & Bypass new PLL dividers */
+ oris r5,r5,0x4000 /*! Set PLL Reset */
+ mtdcr CPC0_PLLMR1,r5 /*! Set clock dividers */
+ rlwinm r5,r5,0,0xBFFFFFFF /*! Clear PLL Reset */
+ mtdcr CPC0_PLLMR1,r5
+/*
+ ! Wait min of 100us for PLL to lock.
+ ! See CMOS 27E databook for more info.
+ ! At 200MHz, that means waiting 20,000 instructions
+*/
+ addi r3,0,20000 /*! 2000 = 0x4e20 */
+ mtctr r3
+pll_wait:
+ bdnz pll_wait
+
+ oris r5,r5,0x8000 /*! Enable PLL*/
+ mtdcr CPC0_PLLMR1,r5 /* ! Engage*/
+
+ /*
+ ! Reset CPU to guarantee timings are OK
+ ! Not sure if this is needed...
+ */
+ b reset_cpu
+
+/*
+ .type pll_write, at function
+ .size pll_write,.-pll_write
+*/
+/*
+!-----------------------------------------------------------------------------
+! Function: reset_cpu
+! Description: Resets the CPU by writing to the DBCR register
+! Input: r3 = none
+! Output r3 = none
+!-----------------------------------------------------------------------------
+*/
+/*
+ .text
+ .align 2
+*/
+ .globl reset_cpu
+
+
+reset_cpu:
+ addis r3,0,0x1000
+ mtspr dbcr0,r3 /*! This will cause a CPU core reset,
and*/
+ /*! execution will continue from the
poweron*/
+ /*! vector of 0xfffffffc*/
+/*
+ .type reset_cpu, at function
+ .size reset_cpu,.-reset_cpu
+*/
+#endif /* (defined(CONFIG_BUBINGA405EP) &&
defined(CONFIG_NO_SERIAL_EEPROM)) */
.globl _start_of_vectors
_start_of_vectors:
llandre
More information about the U-Boot
mailing list