[U-Boot-Users] 440GX PHY/MII access

[Kerl, John]

Hello,

I am wondering if anyone can illuminate the following code snippet,
from ppc_440x_eth_init() in cpu/ppc4xx/440gx_enet.c:

	out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
	__asm__ volatile ("eieio");

	/* reset emac so we have access to the phy */
	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
	__asm__ volatile ("eieio");

	failsafe = 1000;
	while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
		udelay (1000);
		failsafe--;
	}
	in32(EMAC_M0 + hw_p->hw_addr), EMAC_M0 + hw_p->hw_addr);

In particular I don't understand the comment "reset emac so we have
access to the phy".  In fact, print statements before and after
the MAC reset indicate that we *can* read PHY registers before
the MAC reset, but we *lose* the ability to read PHY registers
after the MAC reset.  Note that this does not happen on all
three boards, and not all the time.  Also this loss of PHY-register
access after MAC reset is more likely to happen if the Ethernet cable
is connected.

Now, there are a couple oddities: (1) these are brand-new boards,
still being debugged and flywired; (2) we are using EMACs 2 & 3 over
RGMII, but we have EMACs 0 & 1 not connected to anything (unlike
the Ocotea board).

In particular, I don't doubt that the above code is correct; certainly
the finger of doubt points in the direction of our new board.  Still,
though, I don't yet understand why the MAC reset would cause PHY
access to go away.  The scope reveals that after the MAC reset, the
MDIO line is no longer being driven.

Does this ring any bells for anyone?

Thanks.