[U-Boot-Users] 440GX PHY/MII access

[Kerl, John]

I may be mistaken, but we always avoid strapping PHY addresses
to 0 since this is some sort of broadcast address.  I think this
is an industry-standard fact.  The issues we've been experiencing
(which are most likely due to a board-design issue) persist in
spite of the PHYs having non-zero addresses.

-----Original Message-----
From: u-boot-users-admin at lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net]
Sent: Wednesday, April 14, 2004 5:04 AM
To: Yutao He
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] 440GX PHY/MII access


I don't know of anyway to bypass.  You must restrap
the PHY to a different address.  I used the JTAG
interface to disable all PHYs and the 440GX aways
responds to address zero.

Carl

--- Yutao He <yutao at doremilabs.com> wrote:
> Hi Carl,
> 
> We have a customized 440GX-based board with only
> EMAC2 and EMAC3.
> And the PHY is using address zero. Yes we've got the
> problem with the Ethernet interface. Could you
> please
> shed lights on how to by-pass this "un-documented"
> feature to make EMACS2/3 work?
> 
> Many thanks,
> 
> --Yutao
> 
> Carl Riechers wrote:
> > If you are using address zero for the PHY you will
> > have problems.  The 440GX seems to use this
> address
> > for diagnostics.  I could not find any
> documentation
> > on this.  I have a simular configuration with only
> > eth2 and eth3.  If you are using the Marvel PHYs,
> make
> > sure you hardware reset them per the specification
> > otherwise the soft reset will not work correctly.
> > 
> > The author of the code was most likely using a
> > different brand of PHY and needed to reset the PHY
> to
> > have access to certain registers.  The code
> > reconfigures the selected MAC to interface with
> the
> > serial bus to the PHYs.  Each MAC has a MII serial
> bus
> > master, but only one can drive the MII serial
> > interface to the PHYs though the bridge.
> > 
> > Carl
> > 
> > --- "Kerl, John" <John.Kerl at Avnet.com> wrote:
> > 
> >>Hello,
> >>
> >>I am wondering if anyone can illuminate the
> >>following code snippet,
> >>from ppc_440x_eth_init() in
> cpu/ppc4xx/440gx_enet.c:
> >>
> >>	out32 (ZMII_SSR, ZMII_SSR_SP <<
> >>ZMII_SSR_V(devnum));
> >>	__asm__ volatile ("eieio");
> >>
> >>	/* reset emac so we have access to the phy */
> >>	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
> >>	__asm__ volatile ("eieio");
> >>
> >>	failsafe = 1000;
> >>	while ((in32 (EMAC_M0 + hw_p->hw_addr) &
> >>(EMAC_M0_SRST)) && failsafe) {
> >>		udelay (1000);
> >>		failsafe--;
> >>	}
> >>	in32(EMAC_M0 + hw_p->hw_addr), EMAC_M0 +
> >>hw_p->hw_addr);
> >>
> >>In particular I don't understand the comment
> "reset
> >>emac so we have
> >>access to the phy".  In fact, print statements
> >>before and after
> >>the MAC reset indicate that we *can* read PHY
> >>registers before
> >>the MAC reset, but we *lose* the ability to read
> PHY
> >>registers
> >>after the MAC reset.  Note that this does not
> happen
> >>on all
> >>three boards, and not all the time.  Also this
> loss
> >>of PHY-register
> >>access after MAC reset is more likely to happen if
> >>the Ethernet cable
> >>is connected.
> >>
> >>Now, there are a couple oddities: (1) these are
> >>brand-new boards,
> >>still being debugged and flywired; (2) we are
> using
> >>EMACs 2 & 3 over
> >>RGMII, but we have EMACs 0 & 1 not connected to
> >>anything (unlike
> >>the Ocotea board).
> >>
> >>In particular, I don't doubt that the above code
> is
> >>correct; certainly
> >>the finger of doubt points in the direction of our
> >>new board.  Still,
> >>though, I don't yet understand why the MAC reset
> >>would cause PHY
> >>access to go away.  The scope reveals that after
> the
> >>MAC reset, the
> >>MDIO line is no longer being driven.
> >>
> >>Does this ring any bells for anyone?
> >>
> >>Thanks.
> >>
> >>
> >>
> > 
> >
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