[U-Boot-Users] Having trouble programming u-boot to MPC8560ADS board

Abhijeet Bisain abisain at qualcomm.com
Wed Aug 4 02:19:24 CEST 2004


	I hope this is the right forum to ask this question. I recently received 
the rev A board from Motorola with u-boot and Linux on it and everything is 
nice. But I need to run Montavista linux on it, so I configure u-boot to 
BOOTP and tftp a kernel from them. This works partially fine, I can telnet 
into the machine but there is no console on serial. So I was asked to put a 
u-boot binary from Montavista  onto the board.

	I am using BDI2000 to program the flash but am running into difficulty. 
The config file I have is from Abatron and I haven't modified any Jumpers 
or switches on the board. When I program the flash with u-boot, BDI says it 
was successful, but the data read from the flash is incorrect. The data has 
the first, third, and the eighth bits of a 32 bit word high all the time. 
So a 0x00000000 is seen as 0xa1000000 and a 0x12345678 as 0xb3345678.

	I am attaching the BDI config file below. any help on this will be greatly 


;bdiGDB configuration file for MPC8560ADS
; Move the L2SRAM to the initial MMU page
WM32	0xFF720000      0x68010000      ;L2CTL
WM32	0xFF720100      0xFFFC0000      ;L2SRBAR0
WM32	0xFF720000      0xA8010000      ;L2CTL
; load TLB entries, helper code @ 0xfffff000
WM32    0xfffff000      0x7c0007a4      ;tlbwe
WM32    0xfffff004      0x7c0004ac      ;msync
WM32    0xfffff008      0x48000000      ;loop
; 1MB  TLB1 #1 0x40000000 - 0x400fffff
WSPR    624             0x10010000      ;MAS0:
WSPR    625             0x80000500      ;MAS1:
WSPR    626             0x4000000a      ;MAS2:
WSPR    627             0x40000015      ;MAS3:
WSPR    628             0x00000000      ;MAS4:
EXEC    0xfffff000
; 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff
WSPR    624             0x10020000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0xc0000008      ;MAS2:
WSPR    627             0xc0000015      ;MAS3:
EXEC    0xfffff000
; 64 MB TLB1 #3 0x00000000 - 0x03ffffff
WSPR    624             0x10030000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0x00000008      ;MAS2:
WSPR    627             0x00000015      ;MAS3:
EXEC    0xfffff000
; 64 MB TLB1 #4 0x04000000 - 0x07ffffff
WSPR    624             0x10040000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0x04000008      ;MAS2:
WSPR    627             0x04000015      ;MAS3:
EXEC    0xfffff000
; 16 MB TLB1 #5 0xff000000 - 0xffffffff
WSPR    624             0x10050000      ;MAS0:
WSPR    625             0x80000700      ;MAS1:
WSPR    626             0xff00000a      ;MAS2:
WSPR    627             0xff000015      ;MAS3:
EXEC    0xfffff000
; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff
WSPR    624             0x10000000      ;MAS0:
WSPR    625             0x80000700      ;MAS1:
WSPR    626             0xf0000008      ;MAS2:
WSPR    627             0xf0000015      ;MAS3:
EXEC    0xfffff000
; Remove the L2SRAM from the initial MMU page
WM32	0xFF720000      0x28010000      ;L2CTL
WM32	0xFF720000      0x28000000      ;L2CTL
; Move CCSRBAR to 0x40000000
WM32    0xff700000      0x00040000      ;CCSRBAR to 0x40000000
; Initialize LAWBAR's
WM32    0x40000C08      0x00000000      ;LAWBAR0 : @0x00000000
WM32    0x40000C10      0x80f0001b      ;LAWAR0  : DDR/SDRAM  256MB
WM32    0x40000C28      0x000c0000      ;LAWBAR1 : @0xc0000000
WM32    0x40000C30      0x8040001d      ;LAWAR1  : Local Bus  1GB
; Setup DDR (ADS Rev.Pilot , 128MB DDR)
;WM32    0x40002000      0x00000007      ;CS0_BNDS
;WM32    0x40002080      0x80000002      ;CS0_CONFIG
;WM32    0x40002108      0x37544321      ;TIMING_CFG_1
;WM32    0x4000210C      0x00000800      ;TIMING_CFG_2
;WM32    0x40002110      0x02000000      ;DDR_SDRAM_CFG
;WM32    0x40002118      0x00000062      ;DDR_SDRAM_MODE
;WM32    0x40002124      0x03a30000      ;DDR_SDRAM_IVAL
;DELAY   200
;WM32    0x40002110      0xc2000000      ;DDR_SDRAM_CFG
; Setup DDR (ADS Rev.A , 256MB DDR)
WM32    0x40002000      0x0000000f      ;CS0_BNDS
WM32    0x40002080      0x80000102      ;CS0_CONFIG
WM32    0x40002108      0x36343321      ;TIMING_CFG_1
WM32    0x4000210C      0x00000800      ;TIMING_CFG_2
WM32    0x40002110      0x02008000      ;DDR_SDRAM_CFG
WM32    0x40002118      0x00000062      ;DDR_SDRAM_MODE
WM32    0x40002124      0x045b0100      ;DDR_SDRAM_IVAL
DELAY   200
WM32    0x40002110      0xc2008000      ;DDR_SDRAM_CFG
; Setup Flash chip select
WM32    0x40005000      0xff001801      ;BR0
WM32    0x40005004      0xff006ff7      ;OR0
; Setup flash programming workspace in dual port RAM
WSPR    63              0x40080000      ;IVPR to workspace
WSPR    415             0x000007F0      ;IVOR15 : Debug exception
WM32    0x400807F0      0x48000000      ;write valid instruction
; Setup for program execution
WM32    0x40020000      0x28010000      ;L2CTL
WM32    0x40020000      0x28000000      ;L2CTL
WSPR    63              0x00000000      ;IVPR to workspace
WSPR    406             0x0000700       ;IVOR6  : Program exception
WSPR    415             0x0001500       ;IVOR15 : Debug exception
WM32    0x00000700      0x48000000      ;write valid instruction
WM32    0x00001500      0x48000000      ;write valid instruction
; Clear flash Lock-Bits
WM32    0xFF800000      0x00600060      ;clear Lock-Bits command
WM32    0xFF800000      0x00D000D0
DELAY   1000                            ;needs up to 0.7 sec
WM32    0xFF800000      0xFFFFFFFF      ;set flash to read mode

CPUTYPE     8560        ;the CPU type
JTAGCLOCK   0           ;use 16 MHz JTAG clock
STARTUP     LOOP        ;use boot loop in L2SRAM
;STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   SOFT      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    JTAG        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      200         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms
MEMACCESS   SAP         ;use SAP or CORE for JTAG memory accesses
;REGLIST     E500        ;send registers in E500 sequence to GDB

FILE        /tftpboot/8560/u-boot.bin.8560ads
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DUMP        /tftpboot/8560/e500.bin

CHIPSIZE    0x800000    ;The size of one flash chip in bytes
BUSWIDTH    32          ;The width of the flash memory bus in bits (8 | 16 
| 32)
WORKSPACE   0x40080000	 ;workspace in dual port RAM
;WORKSPACE   0xf0000000 	;workspace in L2SRAM

FILE        /tftpboot/8560/u-boot.bin.8560ads
FORMAT      BIN 0xFFF80000
ERASE       0xFFF80000
ERASE       0xFFFC0000

FILE        /tftpboot/8560/reg8560.def

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