[U-Boot-Users] CPM2 Config Patch
Jon Loeliger
jdl at freescale.com
Mon Dec 6 23:54:16 CET 2004
Wolfgang,
The following patch converts a bunch of CONFIG_<board> references
into a feature-driven reference for the CPM2 on PQ2 and PQ3 boards.
This patch is needed to re-gain consistency of the bd_t structure
for passing CPM2 clocks to Linux. (Also fixes a problem where
the second ethernet address is lost due to the inconsistency.)
Lots of other patches stand between the CVS top from a month
a go and this patch. Please let me know if it doesn't apply
cleanly and I'll regen it for you!
Thanks,
jdl
* Patch by Jon Loeliger, Kumar Gala, 2004-12-03
- Convert the CPM2 based functionality to use new CONFIG_CPM2
option rather than a myriad of CONFIG_MPC8560-like variants.
Applies to MPC85xx and MPC8260 boards, includes stxgp3 and
sbc8560. Eliminates the CONFIG_MPC8560 option entirely.
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/board/cds/mpc8541cds/config.mk internal-development/u-boot-pq3/board/cds/mpc8541cds/config.mk
--- u-boot-public-cvs/u-boot-20041018/board/cds/mpc8541cds/config.mk 2004-10-10 16:21:55.000000000 -0500
+++ internal-development/u-boot-pq3/board/cds/mpc8541cds/config.mk 2004-12-03 16:24:54.000000000 -0600
@@ -27,4 +27,5 @@
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_CPM2=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/board/cds/mpc8541cds/mpc8541cds.c internal-development/u-boot-pq3/board/cds/mpc8541cds/mpc8541cds.c
--- u-boot-public-cvs/u-boot-20041018/board/cds/mpc8541cds/mpc8541cds.c 2004-10-10 16:27:31.000000000 -0500
+++ internal-development/u-boot-pq3/board/cds/mpc8541cds/mpc8541cds.c 2004-12-03 16:24:54.000000000 -0600
@@ -26,6 +26,7 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <ioports.h>
#include <spd.h>
#include "../common/cadmus.h"
@@ -40,6 +41,160 @@
void local_bus_init(void);
void sdram_init(void);
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
int board_early_init_f (void)
{
return 0;
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/board/cds/mpc8555cds/config.mk internal-development/u-boot-pq3/board/cds/mpc8555cds/config.mk
--- u-boot-public-cvs/u-boot-20041018/board/cds/mpc8555cds/config.mk 2004-10-10 16:21:56.000000000 -0500
+++ internal-development/u-boot-pq3/board/cds/mpc8555cds/config.mk 2004-12-03 16:24:54.000000000 -0600
@@ -27,4 +27,5 @@
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_CPM2=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/board/cds/mpc8555cds/mpc8555cds.c internal-development/u-boot-pq3/board/cds/mpc8555cds/mpc8555cds.c
--- u-boot-public-cvs/u-boot-20041018/board/cds/mpc8555cds/mpc8555cds.c 2004-10-10 16:27:31.000000000 -0500
+++ internal-development/u-boot-pq3/board/cds/mpc8555cds/mpc8555cds.c 2004-12-03 16:24:54.000000000 -0600
@@ -24,6 +24,7 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <ioports.h>
#include <spd.h>
#include "../common/cadmus.h"
@@ -38,6 +39,160 @@
void local_bus_init(void);
void sdram_init(void);
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
int board_early_init_f (void)
{
return 0;
Binary files u-boot-public-cvs/u-boot-20041018/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm and internal-development/u-boot-pq3/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm differ
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/board/mpc8560ads/config.mk internal-development/u-boot-pq3/board/mpc8560ads/config.mk
--- u-boot-public-cvs/u-boot-20041018/board/mpc8560ads/config.mk 2004-06-08 19:34:47.000000000 -0500
+++ internal-development/u-boot-pq3/board/mpc8560ads/config.mk 2004-12-03 16:24:58.000000000 -0600
@@ -29,5 +29,5 @@
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_CPM2=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/board/sbc8560/config.mk internal-development/u-boot-pq3/board/sbc8560/config.mk
--- u-boot-public-cvs/u-boot-20041018/board/sbc8560/config.mk 2004-10-10 17:44:34.000000000 -0500
+++ internal-development/u-boot-pq3/board/sbc8560/config.mk 2004-12-03 16:25:00.000000000 -0600
@@ -30,5 +30,5 @@
TEXT_BASE = 0xfffc0000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_CPM2=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/board/stxgp3/config.mk internal-development/u-boot-pq3/board/stxgp3/config.mk
--- u-boot-public-cvs/u-boot-20041018/board/stxgp3/config.mk 2004-04-18 16:45:44.000000000 -0500
+++ internal-development/u-boot-pq3/board/stxgp3/config.mk 2004-12-03 16:25:01.000000000 -0600
@@ -29,5 +29,5 @@
TEXT_BASE = 0xfff80000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_CPM2=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
Only in internal-development/u-boot-pq3: CHANGELOG.moto
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/common/cmd_bdinfo.c internal-development/u-boot-pq3/common/cmd_bdinfo.c
--- u-boot-public-cvs/u-boot-20041018/common/cmd_bdinfo.c 2004-10-10 16:27:32.000000000 -0500
+++ internal-development/u-boot-pq3/common/cmd_bdinfo.c 2004-12-03 16:25:02.000000000 -0600
@@ -68,13 +68,13 @@
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300 */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
print_str ("brgfreq", strmhz(buf, bd->bi_brgfreq));
#endif
print_str ("intfreq", strmhz(buf, bd->bi_intfreq));
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/common/cmd_bootm.c internal-development/u-boot-pq3/common/cmd_bootm.c
--- u-boot-public-cvs/u-boot-20041018/common/cmd_bootm.c 2004-10-10 16:27:32.000000000 -0500
+++ internal-development/u-boot-pq3/common/cmd_bootm.c 2004-12-03 16:25:02.000000000 -0600
@@ -573,7 +573,7 @@
/* convert all clock information to MHz */
kbd->bi_intfreq /= 1000000L;
kbd->bi_busfreq /= 1000000L;
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
kbd->bi_cpmfreq /= 1000000L;
kbd->bi_brgfreq /= 1000000L;
kbd->bi_sccfreq /= 1000000L;
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/cpu/mpc8260/config.mk internal-development/u-boot-pq3/cpu/mpc8260/config.mk
--- u-boot-public-cvs/u-boot-20041018/cpu/mpc8260/config.mk 2003-11-17 15:14:39.000000000 -0600
+++ internal-development/u-boot-pq3/cpu/mpc8260/config.mk 2004-12-03 16:25:04.000000000 -0600
@@ -23,5 +23,5 @@
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_8260 -ffixed-r2 -ffixed-r29 \
+PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \
-mstring -mcpu=603e -mmultiple
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/commproc.c internal-development/u-boot-pq3/cpu/mpc85xx/commproc.c
--- u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/commproc.c 2003-10-15 18:53:51.000000000 -0500
+++ internal-development/u-boot-pq3/cpu/mpc85xx/commproc.c 2004-12-03 16:25:04.000000000 -0600
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/cpm_85xx.h>
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
/*
* because we have stack and init data in dual port ram
* we must reduce the size
@@ -211,4 +211,4 @@
#endif /* CONFIG_POST */
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/cpu_init.c internal-development/u-boot-pq3/cpu/mpc85xx/cpu_init.c
--- u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/cpu_init.c 2003-10-15 18:53:51.000000000 -0500
+++ internal-development/u-boot-pq3/cpu/mpc85xx/cpu_init.c 2004-12-03 16:25:04.000000000 -0600
@@ -30,7 +30,7 @@
#include <ioports.h>
#include <asm/io.h>
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_CPM2
static void config_8560_ioports (volatile immap_t * immr)
{
int portnum;
@@ -115,7 +115,7 @@
memset ((void *) gd, 0, sizeof (gd_t));
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_CPM2
config_8560_ioports(immap);
#endif
@@ -173,7 +173,7 @@
memctl->br7 = CFG_BR7_PRELIM;
#endif
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
m8560_cpm_reset();
#endif
}
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/ether_fcc.c internal-development/u-boot-pq3/cpu/mpc85xx/ether_fcc.c
--- u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/ether_fcc.c 2003-10-15 18:53:51.000000000 -0500
+++ internal-development/u-boot-pq3/cpu/mpc85xx/ether_fcc.c 2004-12-03 16:25:04.000000000 -0600
@@ -48,7 +48,7 @@
#include <config.h>
#include <net.h>
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
@@ -458,4 +458,4 @@
#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/serial_scc.c internal-development/u-boot-pq3/cpu/mpc85xx/serial_scc.c
--- u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/serial_scc.c 2003-10-15 18:53:51.000000000 -0500
+++ internal-development/u-boot-pq3/cpu/mpc85xx/serial_scc.c 2004-12-03 16:25:04.000000000 -0600
@@ -35,7 +35,7 @@
#include <common.h>
#include <asm/cpm_85xx.h>
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
#if defined(CONFIG_CONS_ON_SCC)
#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
@@ -271,4 +271,4 @@
#endif /* CONFIG_CONS_ON_SCC */
-#endif /* CONFIG_MPC8560 */
+#endif /* CONFIG_CPM2 */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/speed.c internal-development/u-boot-pq3/cpu/mpc85xx/speed.c
--- u-boot-public-cvs/u-boot-20041018/cpu/mpc85xx/speed.c 2004-08-01 17:48:20.000000000 -0500
+++ internal-development/u-boot-pq3/cpu/mpc85xx/speed.c 2004-12-03 16:25:04.000000000 -0600
@@ -82,7 +82,7 @@
{
DECLARE_GLOBAL_DATA_PTR;
sys_info_t sys_info;
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
uint sccr, dfbrg;
@@ -94,7 +94,7 @@
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
-#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
gd->scc_clk = gd->vco_out / 4;
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/doc/README.mpc85xxads internal-development/u-boot-pq3/doc/README.mpc85xxads
--- u-boot-public-cvs/u-boot-20041018/doc/README.mpc85xxads 2004-10-10 16:21:57.000000000 -0500
+++ internal-development/u-boot-pq3/doc/README.mpc85xxads 2004-12-03 16:29:06.000000000 -0600
@@ -134,7 +134,6 @@
CONFIG_E500 BOOKE e500 family(Motorola)
CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
CONFIG_MPC8540 MPC8540 specific
- CONFIG_MPC8560 MPC8560 specific
CONFIG_MPC8540ADS MPC8540ADS board specific
CONFIG_MPC8560ADS MPC8560ADS board specific
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/asm-ppc/global_data.h internal-development/u-boot-pq3/include/asm-ppc/global_data.h
--- u-boot-public-cvs/u-boot-20041018/include/asm-ppc/global_data.h 2004-02-23 20:00:13.000000000 -0600
+++ internal-development/u-boot-pq3/include/asm-ppc/global_data.h 2004-12-03 16:25:08.000000000 -0600
@@ -39,7 +39,7 @@
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
/* There are many clocks on the MPC8260 - see page 9-5 */
unsigned long vco_out;
unsigned long cpm_clk;
@@ -56,7 +56,7 @@
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
-#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/asm-ppc/immap_85xx.h internal-development/u-boot-pq3/include/asm-ppc/immap_85xx.h
--- u-boot-public-cvs/u-boot-20041018/include/asm-ppc/immap_85xx.h 2004-10-10 16:21:57.000000000 -0500
+++ internal-development/u-boot-pq3/include/asm-ppc/immap_85xx.h 2004-12-03 16:25:08.000000000 -0600
@@ -1023,9 +1023,7 @@
} ccsr_pic_t;
/* CPM Block(0x8_0000-0xc_0000) */
-#if defined(CONFIG_MPC8540) \
- || defined(CONFIG_MPC8541) \
- || defined(CONFIG_MPC8555)
+#ifndef CONFIG_CPM2
typedef struct ccsr_cpm {
char res[262144];
} ccsr_cpm_t;
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/asm-ppc/u-boot.h internal-development/u-boot-pq3/include/asm-ppc/u-boot.h
--- u-boot-public-cvs/u-boot-20041018/include/asm-ppc/u-boot.h 2004-10-10 16:21:57.000000000 -0500
+++ internal-development/u-boot-pq3/include/asm-ppc/u-boot.h 2004-12-03 16:25:08.000000000 -0600
@@ -51,7 +51,7 @@
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/configs/MPC8541CDS.h internal-development/u-boot-pq3/include/configs/MPC8541CDS.h
--- u-boot-public-cvs/u-boot-20041018/include/configs/MPC8541CDS.h 2004-10-10 16:27:34.000000000 -0500
+++ internal-development/u-boot-pq3/include/configs/MPC8541CDS.h 2004-12-03 16:25:09.000000000 -0600
@@ -33,6 +33,7 @@
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8541 1 /* MPC8541 specific */
#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/configs/MPC8555CDS.h internal-development/u-boot-pq3/include/configs/MPC8555CDS.h
--- u-boot-public-cvs/u-boot-20041018/include/configs/MPC8555CDS.h 2004-10-10 16:27:34.000000000 -0500
+++ internal-development/u-boot-pq3/include/configs/MPC8555CDS.h 2004-12-03 16:25:09.000000000 -0600
@@ -33,6 +33,7 @@
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8555 1 /* MPC8555 specific */
#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/configs/MPC8560ADS.h internal-development/u-boot-pq3/include/configs/MPC8560ADS.h
--- u-boot-public-cvs/u-boot-20041018/include/configs/MPC8560ADS.h 2004-10-10 15:24:00.000000000 -0500
+++ internal-development/u-boot-pq3/include/configs/MPC8560ADS.h 2004-12-03 16:25:09.000000000 -0600
@@ -38,7 +38,7 @@
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
#define CONFIG_PCI
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/configs/SBC8540.h internal-development/u-boot-pq3/include/configs/SBC8540.h
--- u-boot-public-cvs/u-boot-20041018/include/configs/SBC8540.h 2004-10-11 18:10:34.000000000 -0500
+++ internal-development/u-boot-pq3/include/configs/SBC8540.h 2004-12-03 16:25:09.000000000 -0600
@@ -46,7 +46,7 @@
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-#define CONFIG_MPC8560 1 /* MPC8560 (CPU) specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/configs/sbc8560.h internal-development/u-boot-pq3/include/configs/sbc8560.h
--- u-boot-public-cvs/u-boot-20041018/include/configs/sbc8560.h 2004-07-10 18:02:23.000000000 -0500
+++ internal-development/u-boot-pq3/include/configs/sbc8560.h 2004-12-03 16:25:10.000000000 -0600
@@ -40,7 +40,7 @@
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
/* XXX flagging this as something I might want to delete */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/configs/SBC8560.h internal-development/u-boot-pq3/include/configs/SBC8560.h
--- u-boot-public-cvs/u-boot-20041018/include/configs/SBC8560.h 2004-10-11 18:10:34.000000000 -0500
+++ internal-development/u-boot-pq3/include/configs/SBC8560.h 2004-12-03 16:25:09.000000000 -0600
@@ -46,7 +46,7 @@
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-#define CONFIG_MPC8560 1 /* MPC8560 (CPU) specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/configs/stxgp3.h internal-development/u-boot-pq3/include/configs/stxgp3.h
--- u-boot-public-cvs/u-boot-20041018/include/configs/stxgp3.h 2004-08-01 18:03:11.000000000 -0500
+++ internal-development/u-boot-pq3/include/configs/stxgp3.h 2004-12-03 16:25:10.000000000 -0600
@@ -39,7 +39,7 @@
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
#undef CONFIG_PCI /* pci ethernet support */
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/ioports.h internal-development/u-boot-pq3/include/ioports.h
--- u-boot-public-cvs/u-boot-20041018/include/ioports.h 2003-10-15 18:53:55.000000000 -0500
+++ internal-development/u-boot-pq3/include/ioports.h 2004-12-03 16:25:06.000000000 -0600
@@ -25,7 +25,7 @@
* the internal memory map aligns the above structure on
* a 0x20 byte boundary
*/
-#ifdef CONFIG_MPC8560
+#ifdef CONFIG_MPC85xx
#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
#else
#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/include/net.h internal-development/u-boot-pq3/include/net.h
--- u-boot-public-cvs/u-boot-20041018/include/net.h 2004-10-09 16:56:21.000000000 -0500
+++ internal-development/u-boot-pq3/include/net.h 2004-12-03 16:25:07.000000000 -0600
@@ -29,7 +29,7 @@
# endif
#endif /* CONFIG_MPC5xxx */
-#if !defined(CONFIG_NET_MULTI) && (defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_CPM2)
#include <config.h>
#if defined(CONFIG_ETHER_ON_FCC)
#if defined(CONFIG_ETHER_ON_SCC)
diff --exclude=CVS -u -r u-boot-public-cvs/u-boot-20041018/lib_ppc/board.c internal-development/u-boot-pq3/lib_ppc/board.c
--- u-boot-public-cvs/u-boot-20041018/lib_ppc/board.c 2004-10-10 16:21:58.000000000 -0500
+++ internal-development/u-boot-pq3/lib_ppc/board.c 2004-12-03 16:25:11.000000000 -0600
@@ -50,7 +50,7 @@
#include <net.h>
#include <serial.h>
#ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260)||defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
#include <commproc.h>
#endif
#endif
@@ -272,7 +272,7 @@
init_timebase,
#endif
#ifdef CFG_ALLOC_DPRAM
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
dpram_init,
#endif
#endif
@@ -357,7 +357,7 @@
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
-#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
+#if !defined(CONFIG_CPM2)
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#endif
@@ -495,12 +495,12 @@
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
-#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_CPM2)
bd->bi_cpmfreq = gd->cpm_clk;
bd->bi_brgfreq = gd->brg_clk;
bd->bi_sccfreq = gd->scc_clk;
bd->bi_vco = gd->vco_out;
-#endif /* CONFIG_8260 */
+#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC5xxx)
bd->bi_ipbfreq = gd->ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
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