[U-Boot-Users] waiting for timeouts in FPGA code?

[Wolfgang Denk]

In message <403C6563.3020806 at imc-berlin.de> you wrote:
> 
> >>while CFG_FPGA_WAIT{_INIT} is supposed to be the timeout in milliseconds.
> > 
> > Then this design is broken; get_timer() returns the number  of  timer
> > ticks  (= CFG_HZ per second). This is only milliseconds for CFG_HZ ==
> > 1000.
> 
> So I does not matter how fast the timer ticks as long as CFG_HZ is set 
> to the correct value and timeouts are based on CFG_HZ. Correct?

Intheory, yes. Unless CFG_HZ is insane and causes integer arithmetics
overflow.

> > It is supposed to be defined. But many boards define it incorrectly.
> >>Should we use CFG_HZ instead of hardcoded numbers?
> > Definitely.
> 
> Hmm. But that means that when we change e.g. the above mentioned FPGA 
> code to use CFG_HZ that we might break these archictectures !?

Indeed. Do you know a better way? I don't. So  let's  do  this  right
first, and then clean up any mess that you unsheathe.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
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