[U-Boot-Users] waiting for timeouts in FPGA code?

[Wolfgang Denk]

In message <403C99F3.309 at imc-berlin.de> you wrote:
> 
> Here we go:
> 
> * Patch by Steven Scholz, 25 Feb 2004:
>    - Timeouts in FPGA code should be based on CFG_HZ
>    - Minor cleanup in code for Altera FPGA ACEX1K

Added, thanks.

> BTW: I just noticed that loads of timeouts (e.g. CFG_FLASH_ERASE_TOUT) 
> are _not_ defined using CFG_HZ ...

Argh.. :-(

Best regards,

Wolfgang Denk

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