[U-Boot-Users] [PATCH] For MPC 8540/8560 ADS SDRAM Initialization

[Jon Loeliger]

Folks,

The patches that I sent out yesterday had a tiny bug
that only enabled 16 of the 64 Meg of SDRAM.  Apply
this patch to obtain the entire 64 Meg region.

Apply this patch, MPC85XXADS-20040603-diffs with:

    % cd u-boot
    % patch -p0 < path/to/MPC85XXADS-20040603-diffs

Sorry.

jdl


* Patch by Jon Loeliger, 3-Jun-2004
  Fix bug in 8540/8560 ADS to enable all 64Meg of the SDRAM



Index: include/configs/MPC8540ADS.h
===================================================================
RCS file: /cvsroot/u-boot/u-boot/include/configs/MPC8540ADS.h,v
retrieving revision 1.1.1.1.4.9
retrieving revision 1.1.1.1.4.10
diff -u -r1.1.1.1.4.9 -r1.1.1.1.4.10
--- include/configs/MPC8540ADS.h	2004/05/28 19:56:12	1.1.1.1.4.9
+++ include/configs/MPC8540ADS.h	2004/06/03 22:13:19	1.1.1.1.4.10
@@ -182,20 +182,19 @@
 
 /*
  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
- * But each bank is really 16M-bit.  So use a 16MB mask.
  *
  * For OR2, need:
- *    16MB mask for AM, OR2[0:7] = 1111 1111
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
  *		   XAM, OR2[17:18] = 11
  *    9 columns OR2[19-21] = 010
  *    13 rows   OR2[23-25] = 100
  *    EAD set for extra time OR[31] = 1
  *
  * 0    4    8    12   16   20   24   28
- * 1111 1111 0000 0000 0110 1001 0000 0001 = ff006901
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM		0xff006901
+#define CFG_OR2_PRELIM		0xfc006901
 
 #define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
 #define CFG_LBC_LBCR		0x00000000    /* LB config reg */
Index: include/configs/MPC8560ADS.h
===================================================================
RCS file: /cvsroot/u-boot/u-boot/include/configs/MPC8560ADS.h,v
retrieving revision 1.1.1.1.4.10
retrieving revision 1.1.1.1.4.11
diff -u -r1.1.1.1.4.10 -r1.1.1.1.4.11
--- include/configs/MPC8560ADS.h	2004/05/28 19:56:12	1.1.1.1.4.10
+++ include/configs/MPC8560ADS.h	2004/06/03 22:13:19	1.1.1.1.4.11
@@ -185,20 +185,19 @@
 
 /*
  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
- * But each bank is really 16M-bit.  So use a 16MB mask.
  *
  * For OR2, need:
- *    16MB mask for AM, OR2[0:7] = 1111 1111
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
  *		   XAM, OR2[17:18] = 11
  *    9 columns OR2[19-21] = 010
  *    13 rows   OR2[23-25] = 100
  *    EAD set for extra time OR[31] = 1
  *
  * 0    4    8    12   16   20   24   28
- * 1111 1111 0000 0000 0110 1001 0000 0001 = ff006901
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CFG_OR2_PRELIM		0xff006901
+#define CFG_OR2_PRELIM		0xfc006901
 
 #define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
 #define CFG_LBC_LBCR		0x00000000    /* LB config reg */