[U-Boot-Users] Posible IBM PPC440GX Cache Initialization Problem

[VanBaren, Gerald (AGRE)]

This is typically (80% probability) a burst read problem.  RAM tests don't do burst reads.  When you enable cache and start to execute out of it, the cache is filled with a burst read which screws up.  Exception 0700 in this case is caused by reading 0xFFs (a floating point operation) with the FP turned off (or not available in the case of some PPC processors).

Since you say turning off DATA cache fixes the problem, I dropped the burst probability from 99.9999% to 80%.  You may be seeing a problem where you have some self-modifying code and forgot to flush and invalidate the data and instruction caches so what you are executing (icache) is not what you think you are executing (stuck in dcache and not written to memory).

gvb


> -----Original Message-----
> From: u-boot-users-admin at lists.sourceforge.net
> [mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of Carl
> Riechers
> Sent: Thursday, May 06, 2004 9:47 AM
> To: Travis Sawyer
> Cc: u-boot-users at lists.sourceforge.net
> Subject: [U-Boot-Users] Posible IBM PPC440GX Cache Initialization
> Problem
>
>
> I have been getting 0700 exceptions while running
> Linux 2.4.20 on mature code on custom hardware.  I
> discovered that if I call the disable dcache function
> after u-boot relocates to SDRAM the problem is
> corrected.  Apparently the icache is getting
> corrupted.  I don't understand why the dcache affects
> the icache.  I have checked all of the SDRAM timing on
> a GHz occilascope and the waveforms are perfect.  I
> have the ECC on and I can run an exhastive SDRAM test
> with the dcache on.
>
> I was wondering if anyone has seen this problem or if
> I have a hardware problem?
>
> I am currently working on turning on the L2 cache
> using the internal SRAM for benchmarking performance.
>
> Regards,
> Carl J. Riechers
>
>
>
> 
> 	
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