[U-Boot-Users] Accessing a LBC Peripheral thru LCS in MPC8540

[Sudhakar]

Hi All..

I have a problem in Accessing LBC Peripheral [CPLD] connected thru LCS7 in 
MPC8540 based board.

In such case I can get a pulse in the LCS 7 when I use UPM Mode.

But when I use GPCM Mode I couldnt get any pulse..

If anyone knows the answer please pass it on to me.

The steps followed for Accessing the CPLD(LCS 7) in GPCM Mode are as follows
=================================================================
#define CFG_BR7_PRELIM          0xf8000801
#define CFG_OR7_PRELIM          0xffff0ee6
[Detailed BR7/OR7 Setting I have explained below]

I tried accessing the device [CPLD Control Register [Offset 0]]  as below

void
cpldconfig( )
{
  volatile immap_t      *immap = (immap_t *)CFG_IMMR;
  volatile ccsr_lbc_t   *memctl = &immap->im_lbc;
  volatile ushort               *dummy = (uchar *)CFG_CPLD_BASE;        /* set 
all BA bits */
  short x;
  x = *dummy;
  
}
  
=================================================================
We Configured BR7/OR7 as follows

#define CFG_CPLD_BASE   0xF8000000
#define CFG_CPLD_SIZE   0x00010000   /*64 Kbytes */     

#define BRx_PS_8                        0x00000800      /*  8 bit port size                     
*/
#define BRx_MS_GPCM_P   0x00000000      /* G.P.C.M.  Bus Machine Select*/
#define BRx_V                           0x00000001      /* Bank Valid                           
*/

#define ORxG_SCY_14_CLK 0x000000e0      /* 14 clock cycles wait states  */
#define ORxG_CSNT                       0x00000800      /* Chip Select 
Negation Time    */
#define ORxG_ACS_DIV2           0x00000600      /* CS is output 1/2 a clock 
later       */
#define ORxG_TRLX                       0x00000004      /* Timing Relaxed                       
*/
#define ORxG_EHTR                       0x00000002      /* Extended Hold Time 
on Read   */
=================================================================
/*
 * BR7 is configured as follows:
 *
 *     - Base address of 0xF8000000
 *     - 8 bit port size
 *     - Data errors checking is disabled
 *     - Read and write access
 *     - GPCM
 *     - Access are handled by the memory controller according to MSEL
 *     - Not used for atomic operations
 *     - No data pipelining is done
 *     - Valid
 */


#  define CFG_BR7_PRELIM  ((CFG_CPLD_BASE & BRx_BA_MSK)  |\
                                                        BRx_PS_8                         
|\
                                                        BRx_MS_GPCM_P            
|\
                                                        BRx_V)
=================================================================
/* OR7 is configured as follows:
 *
 *     - 64 KB byte
 *     - *BCTL0 is asserted upon access to the current memory bank
 *     - *CW / *WE are negated a quarter of a clock earlier
 *     - *CS is output at the same time as the address lines
 *     - Uses a clock cycle length of 15
 *     - *PSDVAL is generated internally by the memory controller
 *       unless *GTA is asserted earlier externally.
 *     - Relaxed timing is generated by the GPCM for accesses
 *       initiated to this memory region.
 *     - One idle clock is inserted between a read access from the
 *       current bank and the next access.
 */
#define P2SZ_TO_AM(s)   ((~((s) - 1)) & 0xffff8000)     /* must be pow of 2 */

#  define CFG_OR7_PRELIM  (P2SZ_TO_AM(CFG_CPLD_SIZE)           |\
                                                        ORxG_CSNT                      
|\
                                                        ORxG_ACS_DIV2          
|\
                                                        ORxG_SCY_14_CLK        
|\
                                                        ORxG_TRLX                      
|\
                                                        ORxG_EHTR)

=================================================================

-- 
Thanks and Regards,
Sudhakar V

GDA Technologies Ltd.
http://www.gdatech.com