[U-Boot-Users] [PATCH] STXXTC Nand support.
Pantelis Antoniou
pantelis.antoniou at gmail.com
Thu Dec 15 21:11:31 CET 2005
Hi Wolfgang.
The following patch supports the NAND present
on the Silicon Turnkey's XTc board.
The patch is against the testing-NAND branch
of u-boot.
----------8< CHANGELOG 8<------------------
* Support NAND on STXXTC
----------8< patch 8<----------------------
--- a/board/stxxtc/Makefile
+++ b/board/stxxtc/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o oftree.o
+OBJS = $(BOARD).o oftree.o nand.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
--- /dev/null
+++ b/board/stxxtc/nand.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, pantelis.antoniou at gmail.com
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ * (C) Copyright 2005
+ * Dan Malek, Embedded Edge, LLC, dan at embeddededge.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+static void stxxtc_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ volatile immap_t *imap = (volatile immap_t *)CFG_IMMR;
+
+ switch (cmd) {
+ case NAND_CTL_SETNCE:
+ imap->im_ioport.iop_padat &= ~(1 << (15 - 7));
+ break;
+ case NAND_CTL_CLRNCE:
+ imap->im_ioport.iop_padat |= (1 << (15 - 7));
+ break;
+ case NAND_CTL_SETALE:
+ imap->im_ioport.iop_pcdat |= (1 << (15 - 15));
+ break;
+ case NAND_CTL_CLRALE:
+ imap->im_ioport.iop_pcdat &= ~(1 << (15 - 15));
+ break;
+ case NAND_CTL_SETCLE:
+ imap->im_cpm.cp_pbdat |= (1 << (31 - 23));
+ break;
+ case NAND_CTL_CLRCLE:
+ imap->im_cpm.cp_pbdat &= ~(1 << (31 - 23));
+ break;
+ }
+}
+
+/*
+ * chip R/B detection
+ */
+static int stxxtc_nand_ready(struct mtd_info *mtd)
+{
+ volatile immap_t *imap = (volatile immap_t *)CFG_IMMR;
+ return !!(imap->im_ioport.iop_padat & (1 << (15 - 6)));
+}
+
+void board_nand_init(struct nand_chip *nand)
+{
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->hwcontrol = stxxtc_nand_hwcontrol;
+ nand->dev_ready = stxxtc_nand_ready;
+ nand->chip_delay = 18;
+}
+#endif
--- a/board/stxxtc/stxxtc.c
+++ b/board/stxxtc/stxxtc.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2000-2004
- * Pantelis Antoniou, Intracom S.A., panto at intracom.gr
+ * Pantelis Antoniou, Intracom S.A., pantelis.antoniou at gmail.com
* Wolfgang Denk, DENX Software Engineering, wd at denx.de.
* (C) Copyright 2005
* Dan Malek, Embedded Edge, LLC, dan at embeddededge.com
@@ -574,22 +574,6 @@ int board_early_init_f(void)
return 0;
}
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-
-#include <linux/mtd/nand.h>
-
-extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- unsigned long totlen;
-
- totlen = nand_probe(CFG_NAND_BASE);
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -435,88 +435,11 @@
/****************************************************************/
-/* NAND */
-#define CFG_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CFG_MAX_NAND_DEVICE 1
-#undef NAND_NO_RB
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE NAND_BASE
+#define CONFIG_NEW_NAND_CODE
-/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
- } while(0)
-
-#ifndef NAND_NO_RB
-#define NAND_WAIT_READY(nand) \
- do { \
- int _tries = 0; \
- while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
- if (++_tries > 100000) \
- break; \
- } while (0)
-#else
-#define NAND_WAIT_READY(nand) udelay(12)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-/*****************************************************************************/
-
-#define CFG_DIRECT_FLASH_TFTP
-#define CFG_DIRECT_NAND_TFTP
+#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
/*****************************************************************************/
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