[U-Boot-Users] omap2420h4 u-boot debugging CCS JTAG

[Komal Shah]

Richard,

I am trying to debug the omap2420h4 board u-boot
through Code Composer Studio and xds560 JTAG.

I have compiled u-boot with CONFIG_PARTIAL_SRAM
option.

CCS unable to debug after the STR instruction as "sp"
becomes zero:

file: board/omap2420h4/platform.S:
----------------------------------

#ifdef CONFIG_PARTIAL_SRAM
        ldr     sp,     SRAM_STACK
        str     ip,     [sp]    /* stash old link
register */
        mov     ip,     lr      /* save link reg
across call */
...

SRAM_STACK:
        .word LOW_LEVEL_SRAM_STACK

Where LOW_LEVEL_SRAM_STACK equals to 0x4020FFFC .

As per the observation of registers and assembly code
in CCS:
---------------snip-------------------
80E80570 01832100 ORREQ     R2, R3, R0, LSL #2
80E80574 E1A03000 MOV       R3, R0, R0
80E80578 E59FD028 LDR       R13, 0x80E805A8
80E8057C E58DC000 STR       R12, [R13]
80E80580 E1A0C00E MOV       R12, R0, R14
---------------snip-------------------

Where value of R13 becomes zero. And due to that it is
failing at "STR R12, [R13]".

This seems to me the problem in accessing SRAM. Any
hints on debugging the u-boot on the above case would
be usefull for me on porting this code to the board
based on similar core (omap2420). 

=====
---Komal Shah


		
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