[U-Boot-Users] omap2420h4 u-boot debugging CCS JTAG
komal_shah802003 at yahoo.com
Wed Feb 2 17:09:33 CET 2005
--- "Woodruff, Richard" <r-woodruff2 at ti.com> wrote:
> Get an updated u-boot, a pull from the main head
> will result in something better in this regard.
Ok. I have checked out this code and using it for the
> As to your exact failure, I expect your problem is
> procedural at this stage. This bit of code when
from > the bin file, is expected to be
> running in flash, your disasm shows you already
> running in SDRAM, this
> is fine, but you would have had to load the elf file
> to get there...and
Yes. I am running from SDRAM. And loading the "elf"
> this would imply your sdr and gel files have
> everything setup ok, and I
> bet this is not the case.
This is the clock configuration I am using:
APLLs clock input is 12MHz
DPLL settings is 300
CORE_CLK_SRC is 600.0
MPU_FCLK is 300.0
DSP_FCLK is 200.0
DSP_ICLK is 100.0
DSP SYNC is DISABLE(BYPASS)
IVA_FCLK is 200.0
IVA SYNC is DISABLE(BYPASS)
GFX_FCLK is 50.0
L3_CLK is 100.0
L4_CLK is 100.0
Clock Configuration II
Is there anything specific you are expecting for the
gel files to do it?
And in debugging the new cvs code, it gives me
following values for the registers after executing the
80E80554 E59FD024 LDR R13, 0x80E80580
SP(R13) : 0x00000000
R13_SVC : 0x4020FFFC
value at 0x80E80580 is 0x4020FFFC.
But the next instruction
80E80558 E58DC000 STR R12, [R13]
is executed then CCS crashes with the following error:
"Can't single step Target Program: Error
0x00001821/-1025 Error during: command, execution,
timeout, target, and error was encountered within the
emulation driver (PTI), but the precise context is
So, I think it was the first access to SRAM, and it
might had generated the exception ??
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