[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Miles Gazic]

I found one part of the problem.  The 0x8100 I was writing included the
reset bit.  When I take that out I can set the command register and read
it back.  We can now get a link 10Mbps, 100Mbps doesn't work.
Auto-negotiate sometimes doesn't work, and sometimes ends up at 10Mbps
speed even though both sides should do 100Mbps.  We are making progress
now at least.

I went through the register definitions and bit field definitions again
to see if any I am using aren't right for the 440ep, and I noticed that
EMAC_TRTR_128 is 0x01000000 for both 440gx_enet.h and 405gp_enet.h in
U-Boot.  For the EP, only the 5 most significant bits aren't reserved,
and the value in my user manual for EMAC_TRTR_128 is binary 00001.
Seems likely that it's the same for other 440s and 405s, and someone
made a typo.  From the most significant end of the register, 00001... =
0000 1000 = 0x08 != 0x01.  It's page 897 of ppc440ep_um.pdf, and that's the only
user manual I've got.  If anyone has another 440 or 405 user manual
handy and would like to check this out I'd appreciate it.  Otherwise
I'll download a couple other user manuals and if they match mine I'll
figure out how to submit a bug report.

Thanks,
Miles


On Tue, 2005-02-15 at 21:09 -0800, Miles Gazic wrote:
> I'm using a 440EP with MII mode selected, and a Broadcom AC101L phy.
> Autonegotiation was failing, so as an experiment, I tried replacing the
> start of autonegotiation in 440gx_enet.c, with setting the speed
> manually.  I did a miiphy_write to PHY_BMCR (the control register) with
> 0x8100 (which should specify 10mbps, full duplex).  The miiphy_write
> returns  0 which means it doesn't think it failed, but when I look at
> the value in the control register as spit out by miiphy_dump, it is
> still 0x3000 (which is 100mbps and half-duplex), which is the same value
> I always see there.
> 
> I don't think this is just a U-boot problem because I can duplicate
> what's happening using just a Abatron BDI2000.  When I write a
> 0x81002400 into the EMAC_STACR register (which should set the control
> register of the phy to 0x8100), and then write a 0x00001400 into
> EMAC_STACR (which should request a read of the same register), and then
> look at the EMAC_STACR register in the debugger, it has the same 0x3000
> as I see in U-Boot.  It seems likely to me though that if anyone has
> gotten the 440EP to work with MII in U-Boot, then they might be able to
> shed some light on what is going wrong for me.
> 
> Any advice is appreciated,
> Miles