[U-Boot-Users] Enabling caches on MPC8270

Wolfgang Denk wd at denx.de
Mon Feb 28 21:01:06 CET 2005

In message <2c5004c14f78da7fb3bda80a35e456cc at www4.mail.volny.cz> you wrote:
> I am developing a standalone aplication for MPC8270 (PM827 board),
> but I have the U-Boot 1.0.1 for, say, "inspiration" as well. I can
> not force the CPU to use caches. I use the standard (i.e.

This is an old story: enabling instruction cache => using burst  mode
to fetch instructions => stress for the SDRAMs.

> result. CPU either gets 'crazy', decrementing the PC instead of
> incrementing it, or it just doesn't work correctly (for example CRC
> verification, which normally passes through, suddenly doesn't). No

Memory problems?

> address translation mechanism is activated. When I let the U-Boot
> to initialize the CPU, the instruction cache works. Then I can
> reset the CPU, use my initialization code, and it works as well. Is

Memroy problems?

> there some other control of the caches in addition to HID0 and HID2?

You didn't write if you're trying to execute yoiur code  from  SDRAM,
but it sounds is if you would. In this case see the FAQ:

>  Enabling the data cache makes the CPU 'crazy' in either case (i.e.
> even after initialization by the U-Boot). Thanks for any hint.

This is normal on a MPC82xx processor. An explanation can be found in
the README (search for IMMR).

Best regards,

Wolfgang Denk

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Q: Why do PCs have a reset button on the front?
A: Because they are expected to run Microsoft operating systems.

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