[U-Boot-Users] [id]cache_status looks at wrong bit for MPC8560

Murray.Jensen at csiro.au Murray.Jensen at csiro.au
Fri Jul 15 02:40:53 CEST 2005

Hi, the [id]cache_status functions in the MPC85xx start.S code look at
the wrong bit in the L1CSRn registers for the MPC8560. I have a patch
for it, but I was wondering if the code is wrong for all 85xx processors,
or just the 8560. Rather than me downloading all the 85xx user manuals
and checking the register bits (as I am only interested in 8560) I thought
I would post here instead. If anyone knows for certain the code is correct
or otherwise for other 85xx processors, please let me know. Cheers!
Murray Jensen, CSIRO Manufacturing & Infra. Tech.      Phone: +61 3 9662 7763
Locked Bag No. 9, Preston, Vic, 3072, Australia.         Fax: +61 3 9662 7853
Internet: Murray.Jensen at csiro.au

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