[U-Boot-Users] [id]cache_status looks at wrong bit for MPC8560

[Kumar Gala]

If they are wrong on 8560 they are wrong on 85xx since the same code  
is used for all 85xx.

However, looking at the code my guess is that [id]cache_status return  
0 if the caches are off and any non-zero value if they are on.  So  
from that point of view the code appears to be ok.  When you say they  
are looking at the wrong bit, what exactly do you mean?

- kumar

On Jul 14, 2005, at 7:40 PM, <Murray.Jensen at csiro.au>  
<Murray.Jensen at csiro.au> wrote:

> Hi, the [id]cache_status functions in the MPC85xx start.S code look at
> the wrong bit in the L1CSRn registers for the MPC8560. I have a patch
> for it, but I was wondering if the code is wrong for all 85xx
> processors,
> or just the 8560. Rather than me downloading all the 85xx user manuals
> and checking the register bits (as I am only interested in 8560) I
> thought
> I would post here instead. If anyone knows for certain the code is
> correct
> or otherwise for other 85xx processors, please let me know. Cheers!
>
> Murray...
> --
> Murray Jensen, CSIRO Manufacturing & Infra. Tech.      Phone: +61 3  
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