[U-Boot-Users] [id]cache_status looks at wrong bit for MPC8560

[Murray.Jensen at csiro.au]

On Fri, 15 Jul 2005 09:27:49 -0500, Kumar Gala writes:
>When you say they  
>are looking at the wrong bit, what exactly do you mean?

This code:

	srwi    r3, r3, 31      /* >>31 => select bit 0 */

looks at the MSB of L1CSRn. It should look at the LSB.

I think the code should be something like this:

        andi.   r3,r3,1

or maybe:

	li	r4,1
	and	r3,r3,r4

if you dont want to touch CR0 (can you modify the CRs whenever you like?).

This reasoning is based on the description of the L1CSRn regs in my MPC8560
manual. I was wondering if this was correct for all MPC85xx processors, or
just the 8560 (or maybe my manual is wrong, or I haven't seen an errata).
Cheers!
								Murray...
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Murray Jensen, CSIRO Manufacturing & Infra. Tech.      Phone: +61 3 9662 7763
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