[U-Boot-Users] [id]cache_status looks at wrong bit for MPC8560

[Kumar Gala]

On Jul 15, 2005, at 10:36 AM, <Murray.Jensen at csiro.au>  
<Murray.Jensen at csiro.au> wrote:

> On Fri, 15 Jul 2005 09:27:49 -0500, Kumar Gala writes:
>
>> When you say they
>> are looking at the wrong bit, what exactly do you mean?
>>
>
> This code:
>
>     srwi    r3, r3, 31      /* >>31 => select bit 0 */
>
> looks at the MSB of L1CSRn. It should look at the LSB.
>
> I think the code should be something like this:
>
>         andi.   r3,r3,1

This is probably the way to go.

>
> or maybe:
>
>     li    r4,1
>     and    r3,r3,r4
>
> if you dont want to touch CR0 (can you modify the CRs whenever you
> like?).

CR0 is volatile and thus can be used w/o saving it.

I recommend sending a patch to the list to fix this.

- kumar