[U-Boot-Users] Board boots - minor memory controller operation understanding problem

[Peter Asemann]

Hi there!

>>I had the following assumptions:
>>
>>1. The MPC875 will try to boot from 0xfff00100 due to my HRCW settings, 
>>which cause MSR[IP] to be "1".

>>2. The whole memory is tiled with the first 64K of the flash due to the 
>>fact that OR0 is 0x00000ff4 when the board boots, which should mask out 
> 
> 
> Did you read the MPC8xx User's Manual about how the  processor  comes
> up from reset? Read it again, please.

1. I re-read the sections about how the processor comes up from reset.
I still believe that the MPC tries to boot from 0xfff00100 for my board 
is configured that way (plus, it boots my 7-line-assembler-boot-test 
program which is at offset 0xf00100 in my boot flash).

2. I also re-read the section about the memory controller; I didn't read 
anything new, but had an idea that maybe I misinterpreted the way BR[BA] 
and OR[AM] work. My new theory is that the address mask OR[AM] doesn't 
influence the address on the bus (which I thought it could be able to 
before) but only the perception of the memory controller, that means, 
the decision of the memory controller to which memory bank an address 
belongs. Am I right?

Best regards, thanks again for your patience,

Peter Asemann