[U-Boot-Users] Board boots - minor memory controller operation understanding problem

[Wolfgang Denk]

In message <42A060DE.4010000 at web.de> you wrote:
> 
> 2. I also re-read the section about the memory controller; I didn't read 

Widen your scope. Read the section about how the  CPU  comes  out  of
reset.

> anything new, but had an idea that maybe I misinterpreted the way BR[BA] 
> and OR[AM] work. My new theory is that the address mask OR[AM] doesn't 

The question is not how they work in general, but how BR0 /  OR0  are
acting  after  a  reset  until  they  first get written to. [Which is
problaby what your  BDM4GDB  init  script  does,  which  in  turn  is
probably why you don't see the things you expect.]

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
People with narrow minds usually have broad tongues.