[U-Boot-Users] Bug in AT91RM9200: icache not enabled!
Steven Scholz
steven.scholz at imc-berlin.de
Sun Mar 13 15:03:05 CET 2005
Hi there,
while finding out why the loading of my FPGA takes so long with the latest CVS
version of U-Boot I noticed that the icache for the AT91RM9200 is not enabled
although icache_enable() is called in cpu/at91rm9200/start.S:
/*
* This does a lot more than just set up the memory, which
* is why it's called lowlevelinit
*/
bl lowlevelinit /* in memsetup.S */
bl icache_enable;
...
mrc p15, 0, r0, c1, c0, 0
/* Reset bit :Little Endian end fast bus mode */
ldr r3, =0xC0000080
/* Set bit :Asynchronous clock mode, Not Fast Bus */
ldr r4, =0xC0000000
bic r0, r0, r3
orr r0, r0, r4
/* write r0 in cp15 control register (cp15 r1) */
mcr p15, 0, r0, c1, c0, 0
The problem is that icache_enable() only works on bit 2 of CP15 Reg 1. But the
important bit seems to be bit 12 judging by the AT91RM9200 User Manual page 49.
Looking at cpu/arm920t/start.S reveals that bit 12 is set:
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
>>>> orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
So my suggestion is using the above code from cpu/arm920t/start.S for the
AT91RM9200 for consistency in the ARM directories. Explicitly disabling MMU
would not harm. And maybe explicitly enabling "Alignment Fault" would be a good
thing as well.
And maybe we should even fix the functions dcache_{en,dis}able() and
icache_{en,dis}able() in cpu/at91rm9200/cpu.c by introducing
-#define C1_IDC (1<<2) /* icache and/or dcache off/on */
+#define C1_DC (1<<2) /* dcache off/on */
+#define C1_IC (1<<1) /* icache off/on */
just like in cpu/arm920t/cpu.c.
Please comment on this. I am willing to sent appropriate patches.
Thanks a million!
--
Steven
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