[U-Boot-Users] I-cache and D-cache size problem on MPC859

[Sette Agostino]

Hello,

Now I have the U-Boot for MPC859, but I am not sure this line is correct

U-Boot 1.1.3 (Nov 11 2005 - 16:38:24)

CPU:   MPC859TxxZPnnA at 133 MHz: 16 kB I-Cache 8 kB D-Cache FEC present


As far as I know, the I-Cache and the D-Cache of the MPC859 is 4 kB, as
defined in the MPC866UM Appendix F.

Here is the chapter which describe the cache

F.3 Cache Control Registers
The MPC859T bit fields and commands of the cache control and status
registers (IC_CST
and DC_CST) are implemented the same as for the MPC866P. However, the bit
fields of
the cache address registers (IC_ADR and DC_ADR) and the cache data port
registers
(IC_DAT and DC_DAT) must be used for the 4-Kbyte instruction and data
caches. See
Chapter 7, "Instruction and Data Caches."

We think that the MPC859 probably has phisically the same cache size as the
MPC866, but only 4 kB must be used.
Anyway, my question is, must I worry about the data printed on the screen or
can I leave as they are?
I mean, are these information used in other part of the U-Boot or the
Kernel?

Thanks in advance.

Best Regards
Agostino Sette