[U-Boot-Users] cpu/mips/start.S cache config CONF_CM_CACHABLE_NONCOHERENT and CONF_CM_CACHABLE_NO_WA difference

zhuzhenhua zzh.hust at gmail.com
Mon Nov 14 12:21:27 CET 2005

after mips_cache_reset, when i set config as
CONF_CM_CACHABLE_NONCOHERENT, the copy u-boot to sdram in
relocate_code will not succeed, for every 16 bytes, it only last 4
be correct.

but if i set CONF_CM_CACHABLE_NO_WA after mips_cache_reset, the copy
function will work well.but after that, when run in ram, in the line
to get u_boot_end label, it can't get the correct value, if i step in
with BDI2000, it can run to

la t9,board_init_r
jr t9

but the t9 still keep the value
(0xbfcxxxx, which was loaded by
 	la	t9, board_init_f
	j	t9)

and if i add sync before  	la	t9, board_init_f, it can run into
board_init_f, but it load the c functions address not correctly

my questions

1) what the CP0_CONFIG need to set for cache (my core is 4KEC)?
2)  i see before the jump to in_ram, there is some comment as follow:

/* If caches were enabled, we would have to flush them here.

	/* Jump to where we've relocated ourselves.
	addi	t0, a2, in_ram - _start
	j	t0

does it means if i used mips_cache_lock before, i need to add flush code here ?

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